The Lo-tech TRS-80 IDE adapter is an external IDE storage adapter for Tandy TRS-80 model 3/4/4P PCs, enabling connection of standard IDE drives (and CompactFlash cards, with an adapter).

A limitation has been that the machines needed to be booted from floppy disk still, since there is no HDD boot code in the Model 3 and 4 ROMs, and the HDD boot code in the 4P ROM is expecting a WD1010 controller rather than an ATA drive.

Community to the rescue as Audronic, Gazza and Hans have burnt plenty of midnight oil patching the 4P ROM with enough code to get LSDOS 6.3.1 to start up directly from the Lo-tech adapter! Here it is in action:

Currently this has been tested with a number of hard disks (full list in the download) but doesn’t currently work with SD cards. Some DoM devices can though be used, this one having been tested OK. Gazza has kindly put together a RAR achive with the patched ROM binary along with very detailed documentation, which is available via the Lo-tech wiki now.

No more floppy disks needed for your 4P!

Product links have been included here for convenience; Lo-tech has no connection with the sellers.

A thread on vintage-computer.com forum recently caught my eye, member Firebox have breadboarded a simple and low-cost IDE adapter based on a design by Larry Campanell for the TRS-80 Model 4 range, enabling connection of standard IDE drives.  It seemed like an ideal project to turn into a lo-tech PCB.

It turns out there’s already a bootable IDE solution, the FreHD project, providing access to disk images stored on a FAT32 formatted SD card powered by a PIC microcontroller. It does look fantastic, but I felt there could be space for something simpler (and so cheaper) as well.

The prototyped low-cost adapter needs just a few 7400 series ICs, and simply ignores half the data coming from the IDE device to provide the 256-byte sectors the TRS-80 expects. The designer though notes some compatibility issues:

I did have one problem, though — not all IDE drives would work….only one of the four IDE drives I tried would work.

That sounded familiar – I’d been through the same developing the CPLD logic for the XT-CF series.

Timing

When the CPU accesses a device, it first provides the address (IO Port) then the read or write signal.  In the Z80 world the CPU generates the same address, read (RD) and write (WR) signals for memory or IO port addressing, the two being distinguished with IO-Request (IORQ) or Memory Request (MREQ) signals.

In the TRS-80 expansion interface (model 3/4/4P), the system combines IORQ, RD and WR signals to provide simple IN and OUT signals along with the address bus, also providing IORQ and M1 signals for reference which can be used to identify interrupt acknowledgement.

In the original design it seems that device compatibility issues might have been caused by the inclusion of IORQ in the address matching logic:

IORQ is asserted concurrently with IN or OUT, so the logic has a timing issue since the IDE interface expects its chip-select (i.e. address match) line to have been asserted before the read or write command.

The Lo-tech design follows more the the XT-CF design, with the IDE chip-select line being driven directly from the address bus with just an LS688 comparator. Some prototyping work by vcforum member Chromedome45 soon proved the logic – so the Lo-tech TRS-80 IDE Adapter PCB design:

Lo-tech TRS-80 IDE Adapter (image generated with GerbV)

Further information on the board including bill of materials, device drivers and design files can be found on the Lo-tech TRS-80 IDE Adapter wiki page.

Availability

PCBs are available now through the lo-tech shop page.