Lo-tech Wiki - User contributions [en]

Tuning the RaspberryPi Zero2W for Minimum Power Consumption

2026-02-22T11:06:13Z

James: /* See Also */

This guide summarises simple, effective steps to reduce power usage on a Raspberry Pi Zero 2 W. The focus is on headless and always-on use-cases.

Baseline Assumptions:

* Headless system (no HDMI display)
* Raspberry Pi OS Lite
* SSH access available

== Disabling Unused Hardware ==

=== HDMI ===
Disable HDMI output to save ~20–30 mA.

Add to <code>/boot/firmware/config.txt</code>:
<pre>
hdmi_blanking=2
hdmi_force_hotplug=0
hdmi_ignore_hotplug=1
</pre>

=== LEDs ===
Disable the activity and power LEDs if not required.

Add to <code>/boot/firmware/config.txt</code>:
<pre>
dtparam=act_led_trigger=none
dtparam=act_led_activelow=on
</pre>

== Reducing CPU Power ==

=== Limit CPU Frequency ===
Lower the maximum CPU clock to reduce both idle and load power.

Add to <code>/boot/firmware/config.txt</code> (minimum is 600MHz):
<pre>
arm_freq=600
</pre>

=== Limiting Active CPU Cores ===

All Raspberry Pi boards except the Zero(W) and original Raspberry Pi have quad-core CPUs. For many low-power workloads, the system can be limited to two or even one core, so reducing the peak power demand especially during boot.

Edit <code>/boot/firmware/cmdline.txt</code> (keep everything on a single line):

<pre>
maxcpus=2
</pre>

== Reducing Bluetooth and WiFi Power Consumption ==

=== Wi-Fi ===
To disable at boot, add to <code>/boot/firmware/config.txt</code>:
<pre>
dtoverlay=disable-wifi
</pre>

=== Bluetooth ===
To disable at boot, add to <code>/boot/firmware/config.txt</code>:
<pre>
dtoverlay=disable-bt
</pre>

== Tuning the Pi for autostream ==

Lo-tech [https://www.lo-tech.co.uk/autostream/ autostream] is a locally installed service that connects HiFi separates to AirPlay and AirPlay 2 speakers, as is designed around the Pi Zero 2W. To minimise peak and average power consumption in this application:

=== <code>/boot/firmware/cmdline.txt</code> ===

Append (keep everything on a single line):

<pre>
maxcpus=2
</pre>

=== <code>/boot/firmware/config.txt</code> ===

Replace the whole file with this:

<pre>
[all]
# Enable system watchdog
dtparam=watchdog=on

# Disable bluetooth
dtoverlay=disable-bt

# Disable on-board audio
dtparam=audio=off

# Disable camera and DSI display autodetection
camera_auto_detect=0
display_auto_detect=0

# Automatically load initramfs files, if found
auto_initramfs=1

# Run in 64-bit mode
arm_64bit=1

# Fully power down HDMI
hdmi_blanking=2
hdmi_force_hotplug=0
hdmi_ignore_hotplug=1
disable_overscan=1

# Minimum GPU RAM for headless
gpu_mem=16

# Underclock CPU
arm_freq=700
arm_boost=0
force_turbo=0

# Slight undervolt (safe range is usually -2 to -4)
over_voltage=-2

# Zero2Go PSU board parameters
# If you are not using the Zero2Go PSU board, comment these four lines
enable_uart=1
dtparam=i2c1=on
dtparam=i2c_arm=on
dtoverlay=miniuart-bt

</pre>

== Notes ==

* Changes to configuration files require a reboot to take affect
* Test stability if lowering CPU voltage
* If the Pi cannot boot after editing config.txt or cmdline.txt, those files on the SD card can be accessed directly using a Windows PC (or Mac) by connecting the micro-SD card via a USB adapter.

== See Also ==

*[https://www.lo-tech.co.uk/autostream/ autostream (product page)]
*[https://www.lo-tech.co.uk/add-airplay-to-a-vintage-cd-player/ Adding AirPlay to a Vintage CD Player (blog post)]

Tuning the RaspberryPi Zero2W for Minimum Power Consumption

2026-02-22T10:52:33Z

James: /* Limiting Active CPU Cores */ Added configuration for Zero2Go PSU board in autostream config.txt

Tuning the RaspberryPi Zero2W for Minimum Power Consumption

2026-02-20T18:37:26Z

James: /* /boot/firmware/cmdline.txt */ Corrected cmdline parameter to limit CPU cores.

This guide summarises simple, effective steps to reduce power usage on a Raspberry Pi Zero 2 W. The focus is on headless and always-on use-cases.

Baseline Assumptions:

* Headless system (no HDMI display)
* Raspberry Pi OS Lite
* SSH access available

== Disabling Unused Hardware ==

=== HDMI ===
Disable HDMI output to save ~20–30 mA.

Add to <code>/boot/firmware/config.txt</code>:
<pre>
hdmi_blanking=2
hdmi_force_hotplug=0
hdmi_ignore_hotplug=1
</pre>

=== LEDs ===
Disable the activity and power LEDs if not required.

Add to <code>/boot/firmware/config.txt</code>:
<pre>
dtparam=act_led_trigger=none
dtparam=act_led_activelow=on
</pre>

== Reducing CPU Power ==

=== Limit CPU Frequency ===
Lower the maximum CPU clock to reduce both idle and load power.

Add to <code>/boot/firmware/config.txt</code> (minimum is 600MHz):
<pre>
arm_freq=600
</pre>

=== Limiting Active CPU Cores ===

All Raspberry Pi boards except the Zero(W) and original Raspberry Pi have quad-core CPUs. For many low-power workloads, the system can be limited to two or even one core, so reducing the peak power demand especially during boot.

Edit <code>/boot/firmware/cmdline.txt</code> (keep everything on a single line):

<pre>
maxcores=2
</pre>

== Reducing Bluetooth and WiFi Power Consumption ==

=== Wi-Fi ===
To disable at boot, add to <code>/boot/firmware/config.txt</code>:
<pre>
dtoverlay=disable-wifi
</pre>

=== Bluetooth ===
To disable at boot, add to <code>/boot/firmware/config.txt</code>:
<pre>
dtoverlay=disable-bt
</pre>

== Tuning the Pi for autostream ==

Lo-tech [https://www.lo-tech.co.uk/autostream/ autostream] is a locally installed service that connects HiFi separates to AirPlay and AirPlay 2 speakers, as is designed around the Pi Zero 2W. To minimise peak and average power consumption in this application:

=== <code>/boot/firmware/cmdline.txt</code> ===

Append (keep everything on a single line):

<pre>
maxcpus=2
</pre>

=== <code>/boot/firmware/config.txt</code> ===

Replace the whole file with this:

<pre>
# Disable on-board audio
dtparam=audio=off

# Disable camera and DSI display autodetection
camera_auto_detect=0
display_auto_detect=0

# Automatically load initramfs files, if found
auto_initramfs=1

# Run in 64-bit mode
arm_64bit=1

# Disable compensation for displays with overscan
disable_overscan=1

# Enable system watchdog
dtparam=watchdog=on

# Disable bluetooth and UART
dtoverlay=disable-bt
enable_uart=0

# Fully power down HDMI
hdmi_blanking=2
hdmi_force_hotplug=0
hdmi_ignore_hotplug=1

# Underclock CPU
arm_freq=700
arm_boost=0
force_turbo=0

# Minimum GPU RAM for headless
gpu_mem=16

# Slight undervolt (safe range is -2 to -4)
over_voltage=-2
</pre>

== Notes ==

* Changes to configuration files require a reboot to take affect
* Test stability if lowering CPU voltage
* If the Pi cannot boot after editing config.txt or cmdline.txt, those files on the SD card can be accessed directly using a Windows PC (or Mac) by connecting the micro-SD card via a USB adapter.

== See Also ==

*[https://www.lo-tech.co.uk/autostream/ autostream]

Lo-tech ISA CompactFlash Adapter revision 2b

2026-01-24T20:06:20Z

James: /* Design */

The [[Lo-tech ISA CompactFlash Adapter revision 2b]] is a bootable storage adapter for IBM PC, PC/XT, PC/AT and compatible hardware - essentially any PC with an ISA slot. The card enables the use of:

*Standard CompactFlash cards, via any low-cost CompactFlash to IDE adapter
*SD-Cards, via an FC1306T based SD to IDE adapter
*ATA-2 compliant hard disks

<gallery widths="200px" heights="150px" perrow="4">
File:ISA-CompactFlash-Adapter-PCB-Front-r2b.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-front-assembled.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-back.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-back-assembled.JPG
</gallery>

For help getting this kit running, please see the [[Lo-tech ISA CompactFlash Adapter FAQ]] or [{{SERVER}}/get-in-touch/ Get In touch].

The BIOS ROM on the card enables the host PC to boot from storage presented by the adapter, which appears in DOS as an ordinary fixed disk (i.e. drive C, D, etc). No DOS drivers are needed.

The PCB itself is a through-hole, small form factor 8-bit ISA adapter. No slot bracket is needed, due to the small size. The design provides:

*Bootable storage adapter for 8-bit PCs
*Ease of home assembly, by use of only through-hole components for basic operation
*Small form-factor, to enable use in machines with limited expansion slot space such as the Tandy 1000HX, Sinclair PC200 and Amstrad PC-20
*[[IBM Personal Computer XT System Board Slot 8]] compatibility (with optional SMD components mounted on rear of PCB)
*5V supply to IDE header key-pin, for cable-less operation of CompactFlash and SD-Card adapters supporting this power option
*Selectable BIOS address - C800h or D800h

The board is programatically identical to the [[XT-CF-lite]] and uses the [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS], provided through an in-system re-programmable 32KB flash-based ROM. Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable - the board can therefore function as a universal ROM board.

''Please note that ATA and SATA hard drives cannot be used with this adapter, except ATA-2 compliant drives. The [[Lo-tech 8-bit IDE Adapter]] is compatible with standard ATA and SATA drives.''

To buy this and other PCBs, please visit [{{SERVER}}/shop the lo-tech shop].

== Specifications ==

=== General ===

*8-bit ISA card with 40-pin IDE header for attachment to:
**IDE to CompactFlash adapter
**FC1306T based IDE to SD Card adapter
**ATA-2 compliant drives
*5V power supply:
**to IDE header key-pin (can drive micro-drives, CompactFlash adapters and SD Card adapters without any external power connection)
**holes for attachment of peripheral power cable (for use where target host has no available peripheral power cables)
*Basic functionality is dependent only on through-hole components
*Optional SMT components provide additional functionality:
**Line driver for external activity LEDs (12mA power budget for external LED)
**[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Utilises [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS] (adapter type: 'XT-CF')
*Resource requirements:
**IO ports 300-31Fh
**ROM: 32KB at C800h or D800h

== Design ==

<gallery widths="200px" heights="150px" perrow="4">
File:Lo-tech-ISA-CompactFlash-Adapter-rev2b-Schematic.png
File:ISA-CompactFlash-Adapter-PCB-Front-r2b.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-back.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-front-assembled.JPG
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2016 Peacon Ltd (now Lo-tech Systems Limited).

== Bill of Materials ==

=== Core Components ===

Basic functionality requires only through-hole components. JP2 must be closed, and ROM address will be fixed at C800h.

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC3 || 74HCT688N || DIP-20 || 2 || 382504 || 771-74HCT688N
|-
|IC2 || SST39SF010A-70-4C-PHE || DIP-32 || 1 || 1896595 || 804-39SF010A7CPHE
|-
|IC4 || 74HCT139N || DIP-16 || 1 || 382036 || 595-SN74HCT139N
|-
|IC5 || 74HCT245N || DIP-20 || 1 || 9591931 || 595-SN74HCT245N
|-
|RN1 || 4-element Isolated Resistor Network, 10k || SIP-8 || 1 || 9356525 || 652-4608X-2LF-10K
|-
|C1..5 || 0.1uF Ceramic Capacitor || C025-030X050 || 5 || 2112751 || 581-SR205E104MAR or 581-SR205C104KAR
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || 647-UVR1C100MDD
|-
|C8 || 2.2uF Tanalum Capacitor || - || 1 || DNP* || DNP*
|-
|HD1 || T821140A1S100CEU || 2x20 Pin Header, 2.54mm spacing || 1 || 2215314 || 517-30340-6002
|-
|IC Socket (DIP32) || - || DIL32 || 1 || 1654375 || 571-1-2199300-2 517-4832-6000-CP
|-
|IC Socket (DIP20) || - || DIL20 || 3 || 1101349 || 571-1-2199298-6 649-DILB20P-223TLF
|-
|IC Socket (DIP16) || - || DIL16 || 1 || 1101347 || 571-1-2199298-4 649-DILB16P-223TLF
|-
|JP1, JP2, JP3 || - || 1x2 Pin Header || 3 || 1593411 || 855-M20-9990246 653-XG8S-0231
|-
| - || - || 2-pin jumper || 2 || 2396301 || 806-SX1100-A
|}

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
**AMIC chips appear to have been discontinued (as as Nov-13)
*Regardless of the chip used, 32KB is presented at C800h (JP2 closed) or D800h (JP2 open and R4 fitted)
*DNP = Do Not Populate

=== Enhanced Functionality ===

Additional components are required for:

*[[IBM Personal Computer XT System Board Slot 8]] compatibility (also provides enhanced read performance for PC/AT systems)
*Device activity LED
*ROM address selection (C800h/D800h)

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|U1 || SN74LS33D || SOIC-14 || 1 || 1752958 || 595-SN74LS33D
|-
|R1, R2, R4 || RESISTOR, 10K, 125MW || 0805 || 3 || 1612522 || 71-CRCW0805J-10K-E3
|-
|R3 || RESISTOR, 0.125W 1% 270R || 0805 || 1 || 1652970 || 71-CRCW0805270RJNEA
|-
|C7 || CAPACITOR, 0.1UF, 50V || 0805 || 1 || 1612208 || VJ0805V104MXBPW1BC
|-
|LED || - || 1x2 Pin Header || 1 || 1593411 || 855-M20-9990246
|}

Note that when assembling SMT components, additional flux will also be needed (such as Edsyn FL22, Farnell order code 3059091).

== Configuration ==

*JP1: ROM enable (closed = enabled)
*JP2: ROM Address Selection - closed = C800h, open (and R4 fitted) = D800h
*JP3: Slot-8/ZWS Function (closed = enabled) - requires SMT components

An external LED can be attached to the 2-pin LED header only if the optional components (on the rear of the PCB) are populated. Current limit for LED is 12mA.

The IO port address (300h - 31Fh) is fixed.

== Build & Test ==

For additional help, please email me via [{{SERVER}}/get-in-touch/ the site blog].

=== General ===

This project is available in [{{SERVER}}/shop the Lo-tech store] as [{{SERVER}}/product/lo-tech-isa-compactflash-pcb/ a Bare PCB] - components from the Bill of Materials above must be sourced separately for example from Farnell, Newark, Mouser, DigiKey or other electronic component supplier. Farnell and Newark part numbers are provided above for convenience.

An appropriate media adapter and storage device must be purchased separately (i.e. and IDE to CompactFlash adapter and a CompactFlash card).

A temperature controlled soldering iron is highly recommended for assembly. Tin-lead solder is generally easier to use than lead-free. A quality syringe flux is also recommended and is essential for the optional SMT parts (see [[SMT Soldering Notes]]). Before construction, the PCB should be cleaned in isopropynol.

=== Construction ===

*Find a suitable work surface with plenty of light. I find a car-cleaning sponge useful to rest the PCB on since components are held nicely in place under the PCB by the soft surface, which can also be easily turned around as a whole with components not yet soldered
*Start with the least tall components, so that they are held full in place with the solder side up
*When soldering IC sockets or ICs, ensure the notches are at the correct end as indicated by the PCB silkscreen
*If using a shrouded 40-pin header, observe correct orientation as indicated by the silkscreen. The key pin can be removed from the header with a small pair of thin-nose pliers before placement (though note that the key pin can be used to supply 5V to the required CompactFlash adapter if left in-place)
*Note the correct orientation of the polarised capacitors C6 and C8. C8 positive leg is closest to C3.
*Wash all flux residues off once complete using isopropynol (for example with a toothbrush)
*Check closely with a magnifying glass all joints. Check especially for bridges between SMT pins

=== BIOS Flashing (Programming) ===

''The following assumes JP2 is closed, providing the ROM at C800h''

*The board is powered by the [[XTIDE Universal BIOS]] and features a 32KB in-system re-programmable flash chip
*XTIDE Universal BIOS build R560 or newer is recommended (v2 beta 3 is much older)
**[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip Pre-configured BIOS based on R566 - BIOS at C800h]
**[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/offr566.zip Pre-configured BIOS based on R566 - FFh padded with BIOS at CC00h] - see [[Lo-tech_ISA_CompactFlash_Adapter_FAQ#What_BIOS_does_the_Card_Use.3F|FAQ]] for more information
*The flash chip is programmed with the [[Lo-tech XT-CF flash utility]]
*Select the appropriate ROM image:
**IDE_XT.BIN for Intel 8088 and 8086 CPUs
**IDE_XTP.BIN for NEC V20, V30, and Intel 80286 CPUs

'''Note: The late initialisation module in the XTIDE Universal BIOS should only be included in the BIOS build for systems that require this. The module can cause the BIOS to hang after initialisation on other systems. The BIOS build above excludes this module.'''

To program the board, make a DOS boot disk (utilities have been tested on MS-DOS 2.11, 3.3 and 6.22) and add the BIOS binary file and the flash utility. Install the Lo-tech ISA CompactFlash Adapter in the machine and boot from the floppy, then flash the ROM thus:

A:\>flash ide_xt.bin c800

Note that should a board containing the IDE_XTP.BIN image be moved to an Intel 8088/8086 PC, the BIOS image will cause the machine to hang during the POST. To resolve this, either re-flash the board with the IDE_XT.BIN image before moving, or disable the ROM during the POST via JP1. JP1 can be closed once the machine has booted, so enabling the ROM for programming (provided there is no other ROM at C800h).

=== Configuration ===

In addition to the board configurable options, the XTIDE Universal BIOS provides several transfer modes for [[Lo-tech XT-CF Boards]]. The [[Lo-tech ISA CompactFlash Adapter revision 2]] supports two modes (PIO and BIU), which can be changed on-the-fly with the [[Lo-tech XTCFMODE Utility]]. The default mode, set when the BIOS is initialised (i.e. when the machine is powered-on or rebooted), is set within the BIOS via the XTIDE Universal BIOS <tt>xtidecfg.com</tt> utility.

Since the transfer mode reverts at every reboot to the mode set in the BIOS, to permanently set the transfer mode it should be configured accordingly within the BIOS. Alternatively, [[XTCFMODE]] can be included in <tt>AUTOEXEC.BAT</tt>.

For PC/AT class hardware, the use of BIU mode and enabling slot-8/ZWS function (requires optional SMT components and JP3 closed), read performance of up to 1MB/s can be achieved.

== See Also ==

*[[Lo-tech ISA CompactFlash Adapter FAQ]]
*[[lo-tech XT-CF Boards]]

Lo-tech GPIO Interface Board rev.2

2026-01-24T20:06:05Z

James: /* Schematic & Application Notes */

[[File:Lo-tech-gpio-interface-board-rev2-on-RP2.JPG|right|300px]]
The [[Lo-tech GPIO Interface Board rev.2]] enables the connection of the RaspberryPi Model A+/B+/2B/3/4 to the outside world, featuring:

*4x opto-isolated inputs (3.3 ~ 30V)
*8x open-collector outputs (3.3 ~ 30V, 200mA) with inductive drive capability
*Maxim 1-wire bus connection (eg for temperature sensor)
*Fused 5V power header (for powering the Raspberry Pi)

The board has been designed to fit directly on top of the RaspberryPi Model B+ following the HAT physical dimensions (this board does not however provide the I2C EEPROM function required for HAT auto-configuration), and is FCC Class A compliant.

'''Please [{{SERVER}}/get-in-touch/ get in touch.] for a quote for this product.''

== Specifications ==

*Small form-factor:
**Mounts directly to RaspberryPi device and fits within device footprint (65x56mm)
**2.8mm mounting holes aligned with RaspberryPi device mounting holes
**11mm spacing between boards (use 11mm standoff)
*Power Options:
**Power from GPIO header - no separate power connection required; entire device powered via micro-USB on Raspberry Pi
**5V DC provided to screw-terminals on GPIO board - no separate power connection required to the Raspberry Pi. Polyfuse protection is provided (900mA).
*Inputs:
**Four independent opto-isolated inputs with screw terminals
**Input levels: 3.3 ~ 30V
*Outputs:
**Eight Open-Collector outputs with screw terminals
**Optional pull-up resistor on outputs (can be set to 3.3V, 5V, or to external supply via COM terminal)
**Inductive Drive Capable
**Maximum operating frequency: 2MHz
*Maxim 1-wire Bus IO (screw terminals)
*Power LED
*Total assembled weight: 40g (80g, excluding screws, total when mounted on a Raspberry Pi 2)

<gallery widths="150px" heights="125px" perrow="4">
File:lo-tech-gpio-interface-board-front-rev2.jpg
File:lo-tech-gpio-interface-board-front-assembled-rev2.JPG
File:lo-tech-gpio-interface-board-back-rev2.jpg
File:lo-tech-gpio-interface-board-back-assembled-rev2.JPG
</gallery>

''Note: this board does not provide the auto-configuration capabilities defined in the [http://www.raspberrypi.org/introducing-raspberry-pi-hats/ RaspberryPi HAT specification]; GPIOs must be manually configured during program initialisation.''

== Inputs ==

''GPIO numbering follows the BCM numbering''

The board provides four inputs (GPIOs 22, 23, 24, and 27), each interfaced through [http://www.farnell.com/datasheets/1874889.pdf H11L1M opto-isolators], which feature Schmitt Trigger outputs. The inputs require 2mA drive, which should be set via appropriate value of RN1. Inputs can be up to 30V. Inputs are initialised by setting GPIOs 22, 23, 24 and 27 to input mode with pull-up. RN2 provides in-line protection to the GPIO pins.

{|class="wikitable"
!RN1 Value !!Suggested Voltage Range !!Opto Switch-On Voltage (typical) !!Opto Switch-Off Voltage (typical)
|-
|10k || 24 - 30V || 11.3V || 8.9V
|-
|6K8 || 14 - 24V || 8.1V || 6.3V
|-
|3K3 || 7 - 14V || 4.5V || 3.5V
|-
|1K5 || 5 - 7V || 2.6V || 2.2V
|-
|1K || <5V || 2.1V || 1.8V
|}

RN1 is Bourns 4608X-102 type (isolated, 8-pin 4-element)

''Note that this board does not provide transient spike protection - inputs must not exceed 30V. When using pre-production samples, do not set the input channels to output mode with this board connected, as damage to the Raspberry Pi may occur.''

== Outputs ==

''GPIO numbering follows the BCM numbering''

The board outputs are driven by a [http://www.ti.com/lit/ds/symlink/uln2803a.pdf ULN2803A Darlington Transistor Array], which is able to drive inductive loads directly and suppress the kick-back voltage via the internal free wheeling diodes (requires connection of COM terminal to external supply). Initialisation the outputs is achieved by setting GPIOs 5, 6, 12, 13, 16, 19. 20, 21, 26 to output mode.

The eight open-collector outputs are provided via screw terminals, along with GND and COM connections. Should a pull-up be required, RN3 and can added and configured via JP1 to be:

*1-2: 3V3
*2-3: 5V
*Open: when COM is connected.

JP1 '''must''' be open if external supply is connected to COM terminal - Raspberry Pi will be damaged if this is not observed. When JP1 is not open, pull-up current will be sourced from the Raspberry Pi 5V or 3V3 rails, a high value or RN3 should therefore b0e used (typically 10K).

Each output can sink 200mA; however total sink current should not exceed 600mA. ULN2803A power dissipation rules should also be observed (see [http://www.ti.com/lit/ds/symlink/uln2803a.pdf ULN2803a Datasheet]).

When driving inductive loads, external supply should be connected to COM terminal to enable internal free wheeling diodes to suppress kick-back voltage. Operating voltage should also be de-rated to ensure the maximum voltage does not exceed 30V.

== Maxim 1-wire Bus ==

The board 1-wire bus IO is directly connected to GPIO 4, along with a 4K7 pull-up. Connected temperature sensor(s) can be automatically detected by Linux with appropriate kernel modules installed. When devices are cabled, Cat5e cable is recommended.

=== Raspbian Kernel Configuration ===

For 3.18 kernel and newer, a kernel option must be added to <tt>/boot/config.txt</tt> due to change introduced with the Device Tree system (see [http://www.raspberrypi.org/forums/viewtopic.php?t=99263&p=691623 this RaspberyPi Forum Post]). Add this line to the end of the file, and reboot:

<source lang=bash>
dtoverlay=w1-gpio
</source>

Once restarted, kernel modules <tt>w1-gpio</tt> and <tt>w1-therm</tt> need to be installed:

<source lang=bash>
pi@raspberrypi ~ $ sudo modprobe w1-gpio
pi@raspberrypi ~ $ sudo modprobe w1-therm
</source>

This can be made persistent by adding these module names to <tt>/etc/modules</tt>. Sensor data is then available via <tt>/sys/bus/w1</tt>:

<source lang=bash>
pi@raspberrypi /sys/bus/w1 $ find .
.
./devices
./devices/28-000006991886
./devices/w1_bus_master1
./drivers
./drivers/w1_master_driver
./drivers/w1_master_driver/bind
./drivers/w1_master_driver/w1_bus_master1
./drivers/w1_master_driver/uevent
./drivers/w1_master_driver/unbind
./drivers/w1_slave_driver
./drivers/w1_slave_driver/bind
./drivers/w1_slave_driver/28-000006991886
./drivers/w1_slave_driver/uevent
./drivers/w1_slave_driver/unbind
./uevent
./drivers_probe
./drivers_autoprobe
</source>

For [http://datasheets.maximintegrated.com/en/ds/DS18B20.pdf Dallas 18B20 temperature sensors], <tt>28-000006991886</tt> represents the serial-number of the device (also shown in <tt>name</tt>), and the current reading is available in <tt>w1_slave</tt> (28812 in this example is 28.812°C):

<source lang=bash>
pi@raspberrypi /sys/bus/w1/devices/28-000006991886 $ cat name
28-000006991886
pi@raspberrypi /sys/bus/w1/devices/28-000006991886 $ cat w1_slave
cd 01 4b 46 7f ff 03 10 4a : crc=4a YES
cd 01 4b 46 7f ff 03 10 4a t=28812
</source>

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
| C1..C5 || 0.1uF (100nF) || Ceramic Capacitor || THT || 5 || 2112751 || 581-SR205E104MAR
|-
| C6..C7 || 10uF || Electrolytic Capacitor || E2-5 || 2 || 8767084 || 647-UVR1C100MDD
|-
| C8 || Application Dependent || Electrolytic Capacitor || E2-5 || 1 || 8767084 (10uF) || 647-UVR1C100MDD (10uF)
|-
| HD1, HD2 || 10-way screw terminal (3.81mm) || FCI 20020327-D101B01LF or Kobiconn 158-P02EK381V10-E or Multicomp MC000024 || THT || 2 || 2007993 || 649-220327-D101B01LF or 158-P02EK381V10-E
|-
| HD3 || 3-way screw terminal (3.81mm) || FCI 220327-D031B01LF or Kobiconn 158-P02EK381V3-E or Multicomp MC000019 || THT || 1 || 2007986 || 649-220327-D031B01LF or 158-P02EK381V3-E
|-
| F1 || LITTELFUSE 30R135UU. POLYFUSE, PTC, 30V, RADIAL, 900MA || 30R090UU || THT || 1 || 1822234 || 576-30R135UU
|-
| IC1..IC4 || - || H11L1M Optocoupler, Schmitt Trigger || DIP-6 || 4 || 1021127 || 512-H11L1M
|-
| IC5 || - || ULN2803A Darlington Array || DIP-18 || 1 || 1094428 || 511-ULN2803A
|-
| JP1 || - || Pin Header, 1x3 || - || 1 || 1593412 || 855-M20-9990346
|-
| LED || - || 3mm LED || THT || 1 || 1581112 || 645-521-9432F (red) 859-LTL-2231AT (green)
|-
| P1 || - || SOCKET, PCB, 0.1", 20+20WAY || THT || 1 || 7992033 || 855-M20-7832046
|-
| R1 || 270R || 125mW Carbon Film Resistor || THT || 1 || 2329504 || 299-270-RC or 660-CFS1/4CT52R271G
|-
| R2 || 4k7 || 125mW Carbon Film Resistor || THT || 1 || 2329534 || 279-CFR16J4K7
|-
| RN1 || See table* || SIL-8 Resistor Network (Bournes 4608X-102 type) || THT || 1 || See tables || See tables
|-
| RN2** || 1k || 4608X-102-102LF || THT || 1 || 9356517 || 652-4608X-2LF-1K
|-
| RN3 || 10k || SIL-9 Resistor Network (Bournes 4609X-101 type) || THT || 1 || See tables || See tables
|-
| DIL Socket, 8-pin || - || SOCKET, VERTICAL, 1ROW, 8WAY || THT || 1<tt>*</tt> || 3419101 || 571-215297-8 or 571-829265-8
|-
| IC Socket (DIP18) || - || - || DIL18 || 1 || 2445623 || 571-1-2199298-5
|-
| IC Socket (DIP6) || - || - || DIL6 || 4 || 1077343 || 571-1-2199298-1
|}

<tt>*</tt>SIL sockets enable RN1 and RN3 values to be interchanged as required after construction.
<tt>**</tt>Pre-production (engineering sample) boards have RN2 unpopulated.

For values of RN1, see the table in Inputs sections. RN1 component options:

{|class="wikitable"
! Value !! Part !! Farnell !! Mouser
|-
| 1k || 4608X-102-102LF || 9356517 || 652-4608X-2LF-1K
|-
| 1k5 || 4608X-102-152LF || 9356568 || 652-4608X-2LF-1.5K
|-
| 3k3 || 4608X-102-332LF || 9356673 || 652-4608X-2LF-3.3K
|-
| 6k8 || 4608X-102-682LF || 2321777 || 652-4608X-2LF-6.8K
|-
| 10k || 4608X-102-103LF || 9356525 || 652-4608X-2LF-10K
|}

RN3 typically 10K where fitted; other values:

{|class="wikitable"
! Value !! Part !! Farnell !! Mouser
|-
| 1k || 4609X-101-102LF || 9356800 || 652-4609X-1LF-1K
|-
| 1k5 || 4609X-101-152LF || 9356851 || 652-4609X-1LF-1.5K
|-
| 3k3 || 4609X-101-332LF || 9356983 || 652-4609X-1LF-3.3K
|-
| 6k8 || 4609X-101-682LF || 2321778 || 652-4609X-1LF-6.8K
|-
| 10k || 4609X-101-103LF || 9356819 || 652-4609X-1LF-10K
|}

== Schematic & Application Notes ==

<gallery widths="300px" heights="225px" perrow="2">
File:lo-tech-GPIO-Interface-r02-Schematic.png
File:lo-tech-GPIO-Interface-r02-Application-Notes.png
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2014,2015 Peacon Ltd (now Lo-tech Systems Limited).

== Programming ==

Any library suitable for use with the Raspberry Pi (models with 40-pin GPIO header) can be used, for example [http://wiringpi.com/ WiringPi]. The module is compatible with quad-core Pi2. The GPIO channels used are:

{|class="wikitable"
!BCM GPIO !! Purpose !! Notes
|-
|4 || Maxim 1-wire Bus || Screw terminals
|-
|5 || Open-collector Output || Screw terminal output
|-
|6 || Open-collector Output || Screw terminal output
|-
|12 || Open-collector Output || Screw terminal output
|-
|13 || Open-collector Output || Screw terminal output
|-
|16 || Open-collector Output || Screw terminal output
|-
|19 || Open-collector Output || Screw terminal output
|-
|20 || Open-collector Output || Screw terminal output
|-
|22 || Input || See note
|-
|23 || Input || See note
|-
|24 || Input || See note
|-
|26 || Open-collector Output || Screw terminal output
|-
|27 || Input || See note
|}

Note: The specified H11L1M opto-isolator has an LED forward voltage of 1.2V and requires 2mA drive.

== See Also ==

*[http://www.farnell.com/datasheets/1874889.pdf H11L1M Datasheet]
*[http://www.ti.com/lit/ds/symlink/uln2803a.pdf ULN2803a Datasheet]
*[[RaspberryPi Boards]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

XT-CF-lite rev.2

2026-01-24T20:05:46Z

James: /* Design */

[[File:XT-CF-lite-rev2-1536px.jpg|right|300px|Lo-tech XT-CF-lite rev.2, Assembled]]

The lo-tech [[XT-CF-lite rev.2]] is an 8-bit ISA CompactFlash adapter, providing bootable solid-state storage for any IBM compatible PC, including the original [[IBM Personal Computer 5150]]. The board supersedes the [[XT-CF-lite rev.1]].

The CompactFlash card is accessible through a custom-made, 3D printed ISA expansion slot bracket, so it can be exchanged without opening the PC. The slot bracket includes CompactFlash specification guide rails for easy insertion and has a cutout to accommodate both Type I and Type II cards.

The board is based on SOIC 74xx series logic and utilises the 3M N7E50-Q516xx-50 CompactFlash socket, and has been tested with both CompactFlash cards and the Seagate ST1 microdrive.

The board is powered by the [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS], provided through an in-system re-programmable 32KB (addressible) flash-based ROM. Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable.

This PCB is available now in the [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

== Specifications ==

*Bootable 8-bit ISA Storage Adapter with header for single type I or type II CompactFlash or Microdrive media
*Provides fast, fixed-disk storage for 8-bit ISA slot equipped IBM compatible PCs
*Low power consumption and no external power connection required
*[[IBM Personal Computer XT System Board Slot 8]] compatible
*Header for external device activity LED (12mA)
*Low-cost flash memory chip for boot ROM, 32KB usable (24KB available once boot ROM is installed)
*Configurable ROM base address - C800h or D800h
*Configurable IO Port base address - 300h or 320h (change require BIOS flash)
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Utilises [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS] (adapter type: 'XT-CF')

== Design ==

<gallery widths="200px" heights="150px" perrow="4">
File:Lo-tech-xt-cf-lite-rev2-schematic.png
File:lo-tech-xt-cf-lite-rev2-pcb.JPG
File:XT-CF-lite-rev2-1536px.jpg
File:Lo-tech-ISA-Slot-Bracket-Type-2-Guide-Detail.jpg
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. The design is Copyright (c) 2014 Peacon Ltd (now Lo-tech Systems Limited).

For general help with this kit, please see the [[XT-CF-lite FAQ]].

=== Bill of Materials ===

{|class="wikitable"
!Part !! Value !! Package !! Qty !! Farnell !! Mouser !! Digikey
|-
|C1..6 || 0.1uF C-EUC0603 || C0603 || 6 || 1414610 || 963-UMK107BJ104KAHT ||
|-
|C7 || 1uF C-EUC0805 || C0805 || 1 || || 581-0805YD105K ||
|-
|C8 || 22uF CPOL-EUE2-5 || E2-5 || 1 || || 647-UVR1C220MDD1TD ||
|-
|CF1 || N7E50-Q516xx-50 || N7E50-Q516xx-50 || 1 || 1267444 || 517-N7E50-Q516B-50-W || 3M5456CT-ND
|-
|JP1 || PINHD-2X04_2.54-S || 2X04-S || 1 || || 571-5-146256-4 ||
|-
|IC1, IC2 || 74HCT688DW || SO20W || 2 || 1085321 || 771-74HCT688D-T ||
|-
|IC3 || SN74LS33D || SOIC-14 || 1 || 1752958 || 595-SN74LS33D ||
|-
|IC4 || 74ACT245DW || SO20W || 1 || || 595-SN74ACT245DWR ||
|-
|IC5 || 74HCT139D || SOIC-16 || 1 || || 595-SN74HCT139DR ||
|-
|IC6 || SST39SF0x0A || DIP32 || 1 || 1896595 || 804-39SF010A7CPHE ||
|-
|R1 || 270R R-EU_R0603 || R0603 || 1 || || 71-CRCW0603-270-E3 ||
|-
|RN1, RN2 || RESISTOR NETWORK, 10K, ± 2% || 1206 || 2 || 1770137 || 652-CAY16-103J4LF ||
|-
|Socket || || DIL32 || 1 || 1654375 || 517-4832-6000-CP ||
|}

*Board design permits the use of a range of DIP-32 flash chips or 1, 2 or 4Mb:
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
*Regardless of the chip used, the first 32KB only will be mapped into the PC address space
*Base address configuration per [[#Board Configuration|JP1]]

=== Logic ===

The board logic provides three distinct functions:

#ROM Function:
#*IC2 matches the address bus to the selected base address
#*JP1 position 3 being closed, the select signal is fed to the flash-ROM IC6
#CompactFlash interface via IC1, IC4 and IC5
#*IC1 matches the address bus to the selected base address
#*IC4 provides the data bus buffering, to ensure strong signal is driven onto the ISA bus
#*IC5 provides CS0 and CS1 generation based on A4 (alternate status register is at Base+10h) and Reset signal
#Slot-8 Card Select Signal and activity LED drive are generated by IC3
#*R1, RN2 and IC3 can be left unpopulated if slot-8 function and activity LED are not required

=== BIOS Flashing (Programming) ===

*The board is powered by the [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS] and features a 32KB in-system re-programmable flash chip
*XTIDE Universal BIOS build R560 or newer is recommended (v2 beta 3 is much older)
**[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip Pre-configured BIOS based on R566 - BIOS at C800h or D800h]
**[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/offr566.zip Pre-configured BIOS based on R566 - FFh padded with BIOS at CC00h or DC00h] - see [[Lo-tech_ISA_CompactFlash_Adapter_FAQ#What_BIOS_does_the_Card_Use.3F|FAQ]] for more information
*The flash chip is programmed with the [[Lo-tech XT-CF flash utility]]
*Select the appropriate ROM image:
**IDE_XT.BIN for Intel 8088 and 8086 CPUs
**IDE_XTP.BIN for NEC V20, V30, and Intel 80286 CPUs

'''Note: The late initialisation module in the XTIDE Universal BIOS should only be included in the BIOS build for systems that require this. The module can cause the BIOS to hang after initialisation on other systems. The BIOS build above excludes this module.'''

To program the board, make a DOS boot disk (utilities have been tested on MS-DOS 2.11, 3.3 and 6.22) and add the BIOS binary file and the flash utility. Install the Lo-tech ISA CompactFlash Adapter in the machine and boot from the floppy, then flash the ROM thus (assuming JP1 position 1 is closed, so setting the ROM base address to C800h):

A:\>flash ide_xt.bin c800

Note that should a board containing the IDE_XTP.BIN image be moved to an Intel 8088/8086 PC, the BIOS image will cause the machine to hang during the POST. To resolve this, either re-flash the board with the IDE_XT.BIN image before moving, or disable the ROM during the POST by opening JP1 position 3. JP1 position 3 can be closed once the machine has booted, so enabling the ROM for programming (provided there is no other ROM at the selected address).

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_2|Lo-tech ISA Slot Bracket Type 2]].

== Board Configuration ==

[[File:XT-CF-lite-rev2-JP1.png|right|thumb]]
JP1 provides the ROM and IO port base address selection, ROM enable, and LED output.

{| class="wikitable" border="1"
!Position (per silkscreen)
!Function
!Open
!Closed
|-
|1 || ROM Base Address || D800h || C800h
|-
|2 || IO Port Base Address || 320h || 300h
|-
|3 || ROM Function || Disabled || Enabled
|-
|4 || Activity LED || - || -
|}

Default settings are ROM enabled, IO port 300h and ROM base address C800h.

Note that the IO base address is set within the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS] ROM image via the [http://code.google.com/p/xtideuniversalbios/wiki/Manual_v2_0_0#Using_XTIDECFG.COM_(XTIDE_Universal_BIOS_configuration_and_flash Universal BIOS Configuration and Flashing utility]. The IO address set within that utility must match that configured on the card via the DIP switches. Should the IO port address be changed for any reason, the BIOS must be updated and re-flashed (using the [[lo-tech XT-CF flash utility]]).

Device activity LED output is provided at JP1 position 4. Do not short the output. Observe polarity ('+' side is noted on board silkscreen). The LED output is provided through a 270R resistor (R1), providing approx. 12mA.

== See Also ==

*[[XT-CF-lite Technical Reference]]
*[[lo-tech XT-CF Boards]]
*[[XT-CF-lite FAQ]]

Lo-tech GPIO Interface Board

2026-01-24T20:05:31Z

James: /* Schematic */

[[File:Lo-tech-gpio-interface-board-mounted-on-RaspberryPi-Bplus.JPG|right|300px]]
The [[Lo-tech GPIO Interface Board]] enables the connection of the RaspberryPi Model B+ to the outside world, with 4 inputs and 8 outputs. The board has been designed to fit directly on top of the RaspberryPi Model B+ and features low power consumption, being powered directly from the RaspberryPi.

== Specifications ==

*Small form-factor:
**Mounts directly to RaspberryPi device and fits within device footprint (65x56mm)
**2.8mm mounting holes aligned with RaspberryPi device mounting holes
**11mm spacing between boards (use 11mm standoff)
*Powered entirely from GPIO header - no separate power connection required
*Inputs:
**Four independent opto-isolated inputs with screw terminals
**Recommended input levels: 3.3V to 15V
*Outputs:
**Four 5V TTL outputs with screw terminals
**Four on-board LEDs (2-pin headers can be mounted in place of LEDs, if required)
*Single control GPIO control to enable/disable all outputs
*Total assembled weight: 34g (about 85g including RaspberryPi B+ and screws)

<gallery widths="150px" heights="125px" perrow="4">
File:lo-tech-gpio-interface-board-front.JPG
File:lo-tech-gpio-interface-board-front-assembled.JPG
File:lo-tech-gpio-interface-board-back.JPG
File:lo-tech-gpio-interface-board-back-assembled.JPG
</gallery>

''Note: this board does not provide the auto-configuration capabilities defined in the [http://www.raspberrypi.org/introducing-raspberry-pi-hats/ RaspberryPi HAT specification]; GPIOs must be manually configured during program initialisation. Pull-ups are provided where necessary to prevent spurious output values.''

== Inputs ==

''Note: GPIO numbering follows the BCM numbering''

The board provides four inputs (GPIOs 22, 23, 24, and 27), each interfaced through an H11L1M opto-isolator. The inputs require 2mA drive, which should be set via appropriate value of RN1. It is therefore possible to use inputs from almost any low-voltage source (note: never connect mains voltage to this board).

{|class="wikitable"
!Input Logic Level !!RN1 Value
|-
|15V || 6K8
|-
|12V || 4K7
|-
|9V || 3K3
|-
|6V || 2K2
|-
|5V || 1K5
|-
|3.3V || 1K
|}

RN1 is Bourns 4608X-102 type (isolated, 8-pin 4-element)

== Outputs ==

''Note: GPIO numbering follows the BCM numbering''

The board outputs are driven by a 74ACT245N Octal Bus Transceiver. The transceiver gate is controlled by GPIO 21; initialisation process for outputs is:

#Set GPIOs 5, 6, 12, 13, 16, 19. 20, 21, 26 to output mode
#Output value 0 (or 1, as required) to the output channels 5, 6, 12, 13, 16, 19, 20, 26
#Output value 0 to GPIO 21 to enable the bus transceiver

The eight 5V TTL outputs divided into:

*four outputs via screw terminals, for connection to external devices - GPIOs 5, 6, 12, 13
*four outputs to on-board LEDs - GPIOs 16, 19, 20, 26

The total draw across all outputs should not exceed 180mA, and note that power for the outputs is sourced from the RaspberryPi 5V rail.

*Choose RN3 value to match required output impedance (i.e. 100-Ohm)
*Choose RN4 value to provide appropriate current through attached LEDs
*Ensure total current draw will not exceed 180mA
*RN3 and RN4 are Bourns 4608X-102 type (isolated, 8-pin 4-element)

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
| C1..C5 || 0.1uF (100nF) || Ceramic Capacitor || THT || 4 || 2112751 || 594-K104K15X7RF5UH5
|-
| C6, C7 || 10uF || Electrolytic Capacitor || E2-5 || 2 || 8767084 || 647-UVR1C100MDD
|-
| HD1, HD2, HD5 (Farnell parts) || 1x2 Screw Terminal || MULTICOMP MC000045 || THT || 3 || 2008016 || -
|-
| HD3, HD4 (Farnell parts) || 1x2 Screw Terminal || MULTICOMP MC000044 || THT || 2 || 2008015 || -
|-
| HD1, HD2, HD3 (Mouser parts) || 8-way screw terminal (3.81mm) || FCI 20020327-D081B01LF || THT || 1 || - || 649-220327-D081B01LF
|-
| HD4, HD5 (Mouser parts) || 5-way screw terminal (3.81mm) || 20020327-D051B01LF || THT || 1 || - || 649-220327-D051B01LF
|-
| IC1..IC4 || - || H11L1M Optocoupler, Schmitt Trigger || DIP-6 || 4 || 1021127 || 512-H11L1M
|-
| IC5 || - || 74ACT245N Octal Bus Transceiver || DIP-20 || 1 || 1739622 || 595-SN74ACT245N
|-
| LED1..LED5 || - || 3mm LED || THT || 5 || 1581112 || 645-521-9432F (red) 859-LTL-2231AT (green)
|-
| P1 || - || SOCKET, PCB, 0.1", 20+20WAY || THT || 1 || 7992033 || 855-M20-7832046
|-
| R1 || 270R || 125mW Carbon Film Resistor || THT || 1 || 2329504 || 299-270-RC
|-
| R2 || 10k || 125mW Carbon Film Resistor || THT || 1 || 9342419 || 299-10K-RC
|-
| RN1, RN3, RN4 || See table* || SIL-8 Resistor Network (Bournes 4608X-102 type) || THT || 3 || See table* || See table*
|-
| RN2 || 10k || Bournes 4605X-101-103LF || THT || 1 || 9356061 || 652-4605X-1LF-10K
|-
| DIL Socket, 8-pin || - || SOCKET, VERTICAL, 1ROW, 8WAY || THT || 1<tt>*</tt> || 3419101 || 571-215297-8
|-
| IC Socket (DIP20) || - || - || DIL20 || 1 || 1101349 || 571-1-2199298-6
|-
| IC Socket (DIP6) || - || - || DIL6 || 4 || 1077343 || 571-1-2199298-1
|}

<nowiki>*</nowiki>For values of RN1, RN3 and RN4, see tables in Inputs and Outputs sections. Three components are needed for each board, with values chosen to match the desired input voltage levels and output drive current. These components can be changed after construction if SIL-8 sockets are mounted to the board (one socket is specified in the above component list for RN1, since this value is most likely to be changed to interface to different input voltage levels). Component options are:

{|class="wikitable"
! Value !! Part !! Farnell !! Mouser
|-
| 100R || 4608X-102-101LF || 9356509 || 652-4608X-2LF-100
|-
| 270R || 4608X-102-271LF || 9356622 || 652-4608X-2LF-270
|-
| 1k || 4608X-102-102LF || 9356517 || 652-4608X-2LF-1K
|-
| 1k5 || 4608X-102-152LF || 9356568 || 652-4608X-2LF-1.5K
|-
| 2k2 || 4608X-102-222LF || 9356592 || 652-4608X-2LF-2.2K
|-
| 3k3 || 4608X-102-332LF || 9356673 || 652-4608X-2LF-3.3K
|-
| 4k7 || 4608X-102-472LF || 9356703 || 652-4608X-2LF-4.7K
|-
| 6k8 || 4608X-102-682LF || 2321777 || 652-4608X-2LF-6.8K
|}

== Schematic ==

<gallery widths="300px" heights="225px" perrow="1">
File:lo-tech-GPIO-Interface-r01-Schematic.png
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2014 Peacon Ltd (now Lo-tech Systems Limited).

== Programming ==

Any library suitable for use with the Raspberry Pi Model B+ can be used, for example [http://wiringpi.com/ WiringPi]. The GPIO channels used are:

{|class="wikitable"
!BCM GPIO !! Purpose !! Notes
|-
|5 || Output (5V TTL) || Screw terminal output
|-
|6 || Output (5V TTL) || Screw terminal output
|-
|12 || Output (5V TTL) || Screw terminal output
|-
|13 || Output (5V TTL) || Screw terminal output
|-
|16 || Output || Onboard LED
|-
|19 || Output || Onboard LED
|-
|20 || Output || Onboard LED
|-
|21 || Output Control || Output 0 to enable all other outputs; Output 1 to set high-Z state
|-
|22 || Input || See note
|-
|23 || Input || See note
|-
|24 || Input || See note
|-
|26 || Output || Onboard LED
|-
|27 || Input || See note
|}

Note: The specified H11L1M opto-isolator has an LED forward voltage of 1.2V and requires 2mA drive.

== See Also ==

*[[RaspberryPi Boards]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech 8-bit IDE Adapter rev.3

2026-01-24T20:05:17Z

James: /* Design */

[[File:lo-tech-8-bit-ide-adapter-rev3-front.jpg|right|300px|Lo-tech 8-bit IDE Adapter rev.3]]

The [[Lo-tech 8-bit IDE Adapter rev.3]] is a bootable storage adapter for IBM PC, PC/XT, PC/AT and compatible hardware - essentially any PC with an ISA slot. The card enables the use of standard IDE (ATA) and SATA hard drives (via a SATA to IDE bridge).

The BIOS ROM on the card enables the host PC to boot from storage presented by the adapter, which appears in DOS as an ordinary fixed disk (i.e. drive C, D, etc). No DOS drivers are needed.

The PCB itself is a through-hole, 8-bit ISA adapter providing a 40-pin IDE header suitable for connection to one or two disk devices. The design goals were:

*Bootable storage adapter for 8-bit PCs using standard hard disks
*Ease of home assembly, by use of only through-hole components for basic operation
*[[IBM Personal Computer XT System Board Slot 8]] compatibility (with optional SMD components mounted on rear of PCB)
*5V supply to IDE header key-pin, for cable-less operation of Disk-On-Module devices and SATA to IDE Adapters that support this power option
*Equal read and write speed
*Utilise Keystone 9202 ISA slot bracket

The board uses the same ATA register mapping as other Lo-tech XT-CF boards and uses the [http://www.xtideuniversalbios.org/ XT-IDE Universal BIOS] adapter type 'XT-CF (PIO with BIU Offload)' (XT-CF BIU). Note that currently, a specific BIOS build is used, pending integration of changes back into the XTIDE Universal BIOS source. The BIOS is provided through an in-system re-programmable 32KB flash-based ROM operating at either C800h or D800h (user selectable). Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable - the board can therefore function as a universal ROM board.

This PCB is available now in the [{{SERVER}}/product/8-bit-ide-adapter-kit/ Lo-tech PCB Store].

''If only CompactFlash or SD Card storage is required, the [[Lo-tech ISA CompactFlash Adapter revision 2|Lo-tech ISA CompactFlash Adapter]] offers equivalent functionality with a lower component count. This board supercedes the [[Lo-tech 8-bit IDE Adapter rev.2]].''

== Jumper Settings & System Resources ==

*ROM BIOS - 32KB at:
**JP1 Closed, JP2 Closed: C800h
**JP1 Closed, JP2 Open: D800h
*ROM BIOS can be disabled (for example, if a bad flash causes system hang at startup) by opening JP1.
*IO Ports:
**JP3 Closed: 300 to 31Fh
**JP3 Open: 320 to 33Fh

== ROM BIOS & BIOS Flashing ==

*The board is powered by the [http://www.xtideuniversalbios.org/ XT-IDE Universal BIOS] and features a 32KB in-system re-programmable flash chip.
*[{{SERVER}}/downloads/XT-IDE/r567-8-bit-ide-adapter.zip Pre-configured BIOS files] based on XTIDE Universal BIOS R567. Note that this BIOS has been modified for the 8-bit IDE Adapter by disabling the 8-bit media set function (<tt>AH9h_Enable8bitModeForDevice8bitAta</tt>) and is configured for operation with the board configured at 300h.
*The flash chip is programmed with the [[Lo-tech XT-CF flash utility]]
*Select the appropriate ROM image:
**IDE_XT.BIN for Intel 8088 and 8086 CPUs
**IDE_XTP.BIN for NEC V20, V30, and Intel 80286 CPUs

''Note: The late initialisation module in the XTIDE Universal BIOS should only be included in the BIOS build for systems that require this. The module can cause the BIOS to hang after initialisation on other systems. The BIOS build above excludes this module.''

To program the board, make a DOS boot disk (utilities have been tested on MS-DOS 2.11, 3.3 and 6.22) and add the BIOS binary files and the flash utility from the download. Install the Lo-tech 8-bit IDE Adapter in the machine and boot from the floppy, then flash the ROM thus:

A:\>flash ide_xt.bin c800

Note that should a board containing the IDE_XTP.BIN image be moved to an Intel 8088/8086 PC, the BIOS image will cause the machine to hang during the POST. To resolve this, either re-flash the board with the IDE_XT.BIN image before moving, or disable the ROM during the POST via JP1. JP1 can be closed once the machine has booted, so enabling the ROM for programming (provided there is no other ROM at the address selected with JP2).

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
| C1 – C14 || 0.1uF Ceramic Capacitor || C025-030X050 || 14 || 2112751 || 581-SR205E104MAR
|-
| C15, C16 || 22uF Electrolytic Capacitor || E2-5 || 2 || 9451064 || 647-UVR1C220MDD
|-
| HD1 || T821140A1S100CEU || 2x20 Pin Header, 2.54mm spacing || 1 || 2215314 || 517-30340-6002
|-
| IC1, IC3 || 74HCT688N || DIL20 || 2 || 382504 || 771-74HCT688N
|-
| IC2 || SST39SF010ADIP32 || DIL32 || 1 || 1896595 || 804-39SF010A7CPHE
|-
| IC4 || 74HCT139N || DIL16 || 1 || 382036 || 595-SN74HCT139N
|-
| IC5, IC8, IC9 || 74HCT245N || DIL20 || 3 || 9591931 || 595-SN74HCT245N
|-
| IC6, IC7 || 74HCT573N || DIL20 || 2 || 9592091 || 595-SN74HCT573N
|-
| IC10, IC12 || 74HCT32N || DIL14 || 2 || 9591982 || 595-SN74HCT32N
|-
| IC11 || 74HCT02N || DIL14 || 1 || 1740019 || 595-SN74HCT02N
|-
| IC13 || 74HCT04N || DIL14 || 1 || 9591770 || 595-SN74HCT04N
|-
| IC14 || 74LS04N || DIL14 || 1 || 1106072 || 595-SN74LS04N
|-
| JP1, JP2, JP3, LED || PINHD-1X2 || 1X02 || 4 || 1593411 || 855-M20-9990246
|-
| R1, R2, R4, R9 || RESISTOR, 10K, 125MW || 0204/7 || 4 || 9342419 || 270-10K-RC
|-
| R3 || RESISTOR, 1K, 125MW || 0204/7 || 1 || - || 270-1K-RC
|-
| R5 || RESISTOR, 5K6, 125MW || 0204/7 || 1 || - || 270-5.6K-RC
|-
| R6 || RESISTOR, 0.125W 1% 270R || 0204/7 || 1 || 2329504 || 270-270-RC
|-
| R7, R8 || RESISTOR, 10K, 125MW || 0805 || 2 || 1612522 || 71-CRCW0805J-10K-E3
|-
| U1 || 74LS33D || SOIC-14 || 1 || 1752958 || 595-SN74LS33D
|-
| C17 || CAPACITOR, 0.1UF, 50V || 0805 || 1 || 1612208 || VJ0805V104MXBPW1BC
|-
| DIP-14 Socket || - || - || 5 || 1101346 || 571-1-390261-3
|-
| DIP-16 Socket || - || - || 1 || 1101347 || 571-1-390261-4
|-
| DIP-20 Socket || - || - || 7 || 1101349 || 571-1-390261-6
|-
| DIP-32 Socket || - || - || 1 || 1654375 || 571-1-2199300-2
|-
| 2.54mm 2-pin Jumper || - || - || 3 || 1654800 || -
|-
| Keystone 9202 ISA Slot Bracket || - || - || 1 || - || 534-9202
|}

== Design ==

<gallery widths="200px" heights="150px" perrow="4">
File:lo-tech-8-bit-ide-adapter-rev3-schematic.png
File:lo-tech-8-bit-ide-adapter-rev3-front.jpg
File:Lo-tech-8-bit-ide-adapter-rev3-back.JPG
File:lo-tech-8-bit-ide-adapter-rev3-assembled.jpg
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. The design, including the 8- to 16-bit MUX, is Copyright (c) 2015,2016 Peacon Ltd (now Lo-tech Systems Limited).

== ISA Bracket ==

Uses the Keystone 9202 ISA Slot bracket.

== See Also ==

*[[Lo-tech XT-CF Boards]]

Lo-tech 2MB EMS Board

2026-01-24T20:05:00Z

James: /* Design */

[[File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg|right|300px|Lo-tech 2MB EMS Board (r02), Assembled]]
The [[Lo-tech 2MB EMS Board]] is an 8-bit ISA expansion card providing up to 2MB of EMS for [[IBM Personal Computer 5150|IBM compatible PCs]]. The small form factor makes the board suitable for the [[IBM Portable Computer 5155]].

'''This board can now provide XMS for XT class machines''' using [https://mateusz.fr/exms86/ EXMS86, a TSR that provides XMS 2.0 memory services by leveraging an EMS 3.2 source written by Mateusz Viste]. With the authors kind permission, v0.9.7 is also available for download here as [https://lo-tech.co.uk/downloads/exms86/exms86-0.9.7.zip Binaries] and [https://www.lo-tech.co.uk/downloads/exms86/exms86-0.9.7-source.zip Source].

To purchase this board, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

Revision History:

*R01 - Prototype. See [[Lo-tech 2MB EMS Board (prototype) Resources]].
*R02 - First production release.

== Technical Description ==

The [[Lo-tech 2MB EMS Board]] utilises up to four [{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM chips] to provide up to 16Mb (=2MB) total RAM capacity, buffered via a 74ACT245 to ensure compatibility with TTL logic levels, on an 8-bit ISA expansion card. For applications that support EMS, this provides a way to install more than the 1MB total address capacity of the 8086 and 8088 processors.

Following the LIM EMS specification, physical RAM is divided into 16KB pages and addressed via a single 64KB window (the 'page frame') in the [http://en.wikipedia.org/wiki/Upper_memory_area upper memory]. The pages presented within the window are determined by the value set in four page registers, which are programmed through IO ports. A jumper block enables the page frame IO port base addresses to configured to match the system requirements.

For operation, the EMS board requires a LIM memory manager driver, [[LTEMM.EXE]]. This driver provides LIM 4 compatibility.

== XMS Capability ==
The following is included with the kind permission of Mateusz Viste.

''It is a common misconception that XMS is only possible on 386+ machines. XMS (v2.0) is fundamentally a memory-copying API. Applications using XMS do not care where the memory comes from. While XMS is commonly associated with RAM located above the 1 MB boundary (often called "extended memory") on 386+ PCs, that's a historical convention, not a technical requirement. Hence it is perfectly possible for a driver to expose memory via the XMS API even if said memory is not part of the system's RAM - like memory from an EMS board.''

Source: [https://mateusz.fr/exms86/ EXMS86 (EMS-backed XMS)]

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:2MB-EMS-Board-r02-schematic.png
File:2MB-EMS-Board-r02-front.png
File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2014 Peacon Ltd (now Lo-tech Systems Limited).

=== Assembly ===

This PCB makes use of SMT components:

*SOIC chips have a pitch of 1.27mm
*0603 package capacitors and resistors

Assembly requires flux and a temperature controlled soldering station.

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C15 || 0.1uF || X7R Ceramic Capacitor || 0603 || 15 || 1414610 || 80-C0603C104K4R
|-
|C16 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || 140-REA100M1CBK0511P
|-
|IC1, IC5 || - || 74HCT688DW || SOIC-20 || 2 || 1085321 || 771-HCT688D652 or 595-CD74HCT688M
|-
|IC2 || - || 74HCT139D || SOIC-16 || 1 || 1085308 || 771-74HCT139D-T
|-
|IC3 || - || 74HCT04D || SOIC-14 || 1 || 1085299 || 595-SN74HCT04D
|-
|IC4 || - || 74HCT32D || SOIC-14 || 1 || 1201305 || 771-74HCT32D-T
|-
|IC6..IC9 || - || 74HCT573D || SOIC-20 || 4 || 1201309 || 771-74HCT573D
|-
|IC10 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || 771-74HCT245D
|-
|IC11 || - || 74HCT138D || SOIC-16 || 1 || 1201307 || 771-74HCT138D-T
|-
|IC12..IC15 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 4 || 1562901 || 913-AS6C4008-55SIN
|-
|JP1 || - || PINHD-2X4 || - || 1 || 1593441 || 649-77313-101-08LF
|-
|RN1..RN3 || 10k || RESISTOR, ARRAY-4, 10K, 1206 || 1206 || 3 || 1770137 || 652-CAY16-103J4LF
|}

Note: Only one SRAM chip is required to build a functioning board (populate SRAM chips in order from IC12).

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_3|Lo-tech ISA Slot Bracket Type 3]].

== JP1: Board Configuration ==

The board is configured via four jumpers on the pin-header JP1 (O=open, C=closed, position 1 is furthest from IC11 (74LS138D)):

{| class="wikitable"
!Page Frame Base Address !!IO Port Base Address
|-
|
{| class="wikitable"
!Value (1,2) !!Base Address
|-
| C,C || C000h
|-
| O,C || D000h
|-
| C,O || E000h
|-
| O,O || (invalid)
|}
|
{| class="wikitable"
!Value (3,4) !!Base Address
|-
| C,C || 260-263h
|-
| O,C || 264-267h
|-
| C,O || 268-26Bh
|-
| O,O || 26C-26Fh
|}
|-
|}

*The recommended configuration is E000h and 260h, being C,O,C,C.
*The [{{SERVER}}/downloads/2MB-EMS-Board/testems.zip Lo-tech EMS Board Test Utility] can assist with hardware testing after build.

== See Also ==

*[[Lo-tech Memory Boards]]
*[[Lo-tech Memory Board FAQ]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech 2MB EMS Board (prototype) Resources

2026-01-24T20:04:14Z

James: /* Design */

Resources on this page are for the Lo-tech 2MB EMS Board (prototype).

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:Lo-tech-2MB-EMS-Board-schematic.png
File:Lo-tech-2MB-EMS-board-pcb.JPG
File:Lo-tech-2MB-EMS-Board-assembled.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013 Peacon Ltd (now Lo-tech Systems Limited).

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C15 || 0.1uF || X7R Ceramic Capacitor || 0603 || 15 || 1414610 || -
|-
|C16 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || -
|-
|IC1, IC5 || - || 74HCT688DW || SOIC-20 || 2 || 1085321 || -
|-
|IC2 || - || 74HCT139D || SOIC-16 || 1 || 1085308 || -
|-
|IC3 || - || 74HCT04D || SOIC-14 || 1 || 1085299 || -
|-
|IC4 || - || 74HCT32D || SOIC-14 || 1 || 1201305 || -
|-
|IC6..IC9 || - || 74HCT573D || SOIC-20 || 4 || 1201309 || -
|-
|IC10 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || -
|-
|IC11 || - || 74HCT138D || SOIC-16 || 1 || 1201307 || -
|-
|IC12..IC15 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 4 || 1562901 || -
|-
|JP1 || - || PINHD-2X4 || - || 1 || 1593441 || -
|-
|RN1 || 10k || BOURNS 4609X-101-103LF || SIL-9 || 1 || 2112931 || -
|-
|RN2 || 10k || BOURNS 4605X-101-103LF || SIL-5 || 1 || 9356061 || -
|}

== JP1: Board Configuration ==

The board is configured via four jumpers on the pin-header JP1 (O=open, C=closed, position 1 is furthest from IC11 (74LS138D)):

{| class="wikitable"
!Page Frame Base Address !!IO Port Base Address
|-
|
{| class="wikitable"
!Value (1,2) !!Base Address
|-
| C,C || C000h
|-
| O,C || D000h
|-
| C,O || E000h
|-
| O,O || F000h
|}
|
{| class="wikitable"
!Value (3,4) !!Base Address
|-
| C,C || 040-043h
|-
| O,C || 060-063h
|-
| C,O || 240-243h
|-
| O,O || 260-263h
|}
|-
|}

The recommended configuration is E000h and 260h, being C,O,O,O. Note that F000h cannot be used due to the system BIOS occupying this physical segment.

== See Also ==

*[[Lo-tech 2MB EMS Board]] (current version)

Lo-tech Yamaha C1 Music Computer IDE Adapter

2026-01-24T20:04:00Z

James: /* Design */

[[File:Yamaha-C1-IDE-Assembled-Front.jpg|right|300px|Lo-tech Yamaha C1 IDE Adapter]]

The [[Lo-tech Yamaha C1 Music Computer IDE Adapter]] is a bootable storage adapter specifically for the Yamaha C1 music computer. The product consists of a specific disk controller PCB, pictured, and a patched system ROM provided as a pair of 27C256 ROM images, including the [[XTIDE Universal BIOS]].

This adapter is a 16-bit IDE interface and is compatible with all 16-bit ATA devices (standard hard drives, SD-Cards or SATA drives via an adapter, or CompactFlash).

The C1 was supplied either with dual floppy drives, or one floppy and an MFM HDD. The PCB itself is a through-hole design and replaces the Yamaha MFM controller daughter board (fitted in HDD equipped models).

The board uses standard ATA register mapping and uses the [http://www.xtideuniversalbios.org/ XT-IDE Universal BIOS] configured for generic 16-bit IDE controller at 1F0h. The XTIDE Universal BIOS itself has been integrated into the custom system ROM images provided below.

'''This PCB is available to order from [https://texelec.com/product/lo-tech-yamaha-c1-music-computer-ide-adapter/ TexElec].'''

== Jumper Settings & System Resources ==

*ROM BIOS - integrated into Yamaha system ROM (see [[#Downloads|Downloads]], below):
*IO Ports: Standard IDE port mapping, 1F0h.

=== Jumper Settings ===

{| class="wikitable" border="1"
|-
!Jumper
!Description
!Default
|-
| JP1 || Enables disk in use signal generation when closed. Required to light C1 HDD activity LED. || Closed
|-
| JP2 || Generates IDE Reset from host when closed. || Closed
|-
| JP3 || Source for IDE Reset signal - 1-2 = ISA Reset, 2-3 = Powerfail || 2-3
|-
| JP4 || Enable IDE Pin-20 Power || Open
|}

== System ROM BIOS & BIOS Flashing ==

The board is powered by the [http://www.xtideuniversalbios.org/ XT-IDE Universal BIOS] via integration with a custom system ROM available from the [[#Downloads|Downloads]] section below. The system BIOS chips cannot be programmed in-system; the two 27C256 chips (IC39 and IC40) must be removed from the system for programming (or replaced with ready-programmed chips).

The custom BIOS includes the XTIDE Universal BIOS in free space. The built-in option ROM scan has been extended into the F segment to provide initialisation.

Due to the 16-bit architecture of the machine, the ROM image is stored byte-interleaved between the two chips.

== Yamaha C1 System Board Configuration ==

The Yamaha C1 has two DIP switch blocks - Switch block 1, on the rear panel of the machine and Switch block 2, on the system board under the keyboard. Use of this adapter requires that Switch Block 2 is configured as for the HDD model. Switch Block 2 is documented in the service manual on page 7:

{|class="wikitable"
!Switch
!Function
!On
!Off
|-
| 1 || FDD-Selects the floppy disk or the Hard disk model. || Floppy Disk Model || Hard Disk Model
|-
| 2 || HDD-Selects the floppy disk or the Hard disk model. || Hard Disk Model || Floppy Disk Model
|-
| 3 || Bit 6 of the system configuration information. || N/A || Default (Yamaha C1)
|-
| 4 || Bit 7 of the system configuration information || N/A || Default (Yamaha C1)
|}
== Installation Procedure ==

#Open the machine and remove the keyboard, being careful to avoid damage to the clear plastic ribbon connectors under the numeric keypad
#Remove the factory RLL controller and hard disk, if fitted
#Remove the second floppy disk drive (the lower drive) if fitted. The remaining floppy drive must be connected on the twisted connector at the end of the floppy cable
#Remove the system ROM chips C39 and C40 (under the keyboard), and re-flash or replace with the system specific code provided.
#Re-fit the system ROM chips
#Note the positions of switches on Switch Block 2 for future reference.
#Set on Switch Block 2: 1=off, 2=on, 3=off, 4=off
#Attach the IDE ribbon cable to the Lo-tech adapter, and set the jumpers as required
#Install the adapter and route the IDE cable as required
#Install an IDE HDD or other storage (CompactFlash etc) as required, and connect to the adapter and to power
#Re-assemble the machine
#Power-on the machine, enter the BIOS configuration utility (CTRL-ALT-S)
##Set the fixed disk type to "Not Installed"
##Set the second floppy drive to "Not Installed"
#Boot the machine from an MS-DOS boot disk and proceed with Hard Disk configuration (FDISK, FORMAT etc)

== Design ==

<gallery widths="200px" heights="150px" perrow="4">
File:Lo-tech-Yamaha-C1-HDD-Schematic-r01.png
File:Yamaha-C1-HDD-PCB-r01.png
File:Yamaha-C1-IDE-Assembled-Front.jpg
File:Yamaha-C1-IDE-Assembled-Back.jpg
File:C1-XUB-Boot.jpg
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. The design is Copyright (c) 2019,2022 Peacon Ltd (now Lo-tech Systems Limited). Assembled board images are Copyright (c) 2019, TexElec.

== Downloads ==

*[https://www.lo-tech.co.uk/downloads/Yamaha-C1/Yamaha-C1-ROMs.zip System ROM binaries]
*[{{SERVER}}/downloads/Yamaha-C1/Yamaha_C1_Service_Manual.pdf Yamaha C1 Service Manual]
*[https://www.lo-tech.co.uk/downloads/Yamaha-C1/Yamaha_C1_Operating_Manual.pdf Yamaha C1 Operating Manual]
*[https://www.lo-tech.co.uk/downloads/Yamaha-C1/schematic_sections_opt.pdf Yamaha C1 Schematics]

== See Also ==

*[[Lo-tech XT-CF Boards]]
*[[Main Page]]

Lo-tech 1MB RAM Board

2026-01-24T20:03:33Z

James: /* Design */

[[File:Lo-tech-1MB-RAM-Board-assembled-r02.jpg|right|300px|Lo-tech 1MB RAM Board (r02), Assembled]]
The [[Lo-tech 1MB RAM Board]] is an 8-bit ISA expansion card providing up to 1MB of system RAM to [[IBM Personal Computer 5150|IBM compatible PCs]]. The small form factor makes the board suitable for the [[IBM Portable Computer 5155]].

This board can be purchased online via [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

Revision History:

*R01 - Prototype. See [[Lo-tech 1MB RAM Board (prototype) Resources]].
*R02 - First production release.

== Technical Description ==

The [[Lo-tech 1MB RAM Board]] utilises two [{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM chips] to provide 8Mb (=1MB) total RAM capacity, buffered via a 74HCT245 to ensure compatibility with TTL logic levels, on an 8-bit ISA expansion card.

DIP switches enable each 64KB physical page to be independently enabled, so making possible RAM expansion of all systems to the maximum 640KB, regardless of the size of the system board RAM fitted. To extend compatibility further, the first 16KB can be excluded, so providing compatibility with the [[IBM Personal Computer 5150]] when the system board is populated with the minimum 16KB RAM.

The board can also provide [http://en.wikipedia.org/wiki/Upper_memory_area upper memory] (between 640KB and 1MB) that, whilst not generally used by MS-DOS in an XT class machine, can be used for specific purposes such as TSRs, disk cache and print spoolers. Any complete unused physical pages can be populated by the RAM board for this purpose.

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:Lo-tech-1MB-RAM-Board-schematic-r02.png
File:1MB-RAM-Board-r02-Top.png
File:Lo-tech-1MB-RAM-Board-assembled-r02.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2014 Peacon Ltd (now Lo-tech Systems Limited).

=== Assembly ===

This PCB makes use of SMT components:

*SOIC chips have a pitch of 1.27mm
*0603 package capacitors and resistors

Assembly requires flux and a temperature controlled soldering station.

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C9 || 0.1uF || X7R Ceramic Capacitor || 0603 || 9 || 1414610 || C0603C104K4RACTU
|-
|C10 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || 140-REA100M1CBK0511P
|-
|IC1, IC2 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 2 || 1562901 || 913-AS6C4008-55SIN
|-
|IC3, IC4 || - || 74HCT138D || SOIC-16 || 2 || 1201307 || 771-74HCT138D-T
|-
|IC5, IC6 || - || 74HCT30D || SOIC-20 || 2 || 1085303 || 771-HCT30D652
|-
|IC7 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || 771-74HCT245D
|-
|IC8 || - || 74LS05D || SOIC-14 || 1 || 9592164 || 595-SN74LS05D
|-
|IC9 || - || 74HCT02D || SOIC-14 || 1 || 1085298 || 595-SN74HCT02D
|-
|RN1..RN5 || 10k || RESISTOR, ARRAY-4, 10K, 1206 || 1206 || 5 || 1770137 || 652-CAY16-103J4LF
|-
|SW1, SW2 || - || MULTICOMP MCNDS-08-V || DIP-16 || 2 || 9471596 || 774-2068
|}

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_3|Lo-tech ISA Slot Bracket Type 3]].

== DIP Switch Settings ==

The board is configured via two banks of DIP switches, which control whether each physical segment (=64KB) is active on the memory board.

Switch position ON enables the corresponding page:

{| class="wikitable"
!Sw1 !!Sw2
|-
|
{| class="wikitable"
!Position !!Page !! Memory Range
|-
| 1.1 || 0000h || 0-64KB (16-64KB when Sw2.8 ON)
|-
| 1.2 || 1000h || 64-128KB
|-
| 1.3 || 2000h || 128-192KB
|-
| 1.4 || 3000h || 192-256KB
|-
| 1.5 || 4000h || 256-320KB
|-
| 1.6 || 5000h || 320-384KB
|-
| 1.7 || 6000h || 384-448KB
|-
| 1.8 || 7000h || 448-512KB
|}
|
{| class="wikitable"
!Position !!Page !! Memory Range
|-
| 2.1 || 8000h || 512-576KB
|-
| 2.2 || 9000h || 576-640KB
|-
| 2.3 || A000h || 640-704KB
|-
| 2.4 || B000h || 704-768KB
|-
| 2.5 || C000h || 768-832KB
|-
| 2.6 || D000h || 832-896KB
|-
| 2.7 || E000h || 896-960KB
|-
| 2.8 || - || Disables 0-16KB (when Sw1.1 ON)
|}
|-
|}
Note that when used with IBM 5150 16-64KB system board, the system board should be populated with 64KB to avoid bus contention.

== See Also ==

*[[Lo-tech Memory Boards]]
*[[Lo-tech Memory Board FAQ]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Terms and Conditions

2026-01-24T19:57:49Z

James: Updated to reflect change of company name.

== Licensed Use: Web Content and Downloads ==

Web Content available via '''lo-tech.co.uk''' is provided for non-commercial use with the license as set out as follows.

; Owner :The '''lo-tech''' and '''lo-tech.co.uk''' brands are trading names of [[Lo-tech Systems Limited]]. The use of the '''Lo-tech''' and '''Lo-tech.co.uk''' brands are restricted by [[Copyrights|Copyright]].
;Restriction Of Use:'''Lo-tech.co.uk''' designs (both hardware and software) are intended to provide interesting insight into electronics and the workings of computers. They are not fault tolerant and are not designed or intended for use in control equipment in hazardous environments requiring fail-safe performance, such as industrial machinery, in which the failure of such components could lead to death or personal injury. Product-specific and general [[Warnings]] should be observed.
;Commercial Use Limitation:Where '''Lo-tech.co.uk''' designs (both hardware and software) are provided in source-code format (i.e. 'Open Source'), this material is provided for the benefit of the hobbyist end-user, and must not be used in a way that competes with products or services provided via Lo-tech.co.uk. Circuit schematics, whether provided in a CAD software native format or as an image file, are considered to be Open Source in this context. [[Copyrights]] should also be observed.
;Indemnity
:The user will indemnify and hold [[Lo-tech Systems Limited]] and its related companies harmless for, from and against, any claims or liabilities, including without limitation product liability claims, arising out of the use, reproduction or distribution of Software, Hardware, Documentation, and parts thereof.
; Limited Warranty and Limited Liability:Where software, hardware, or documentation is provided free of charge, it is provided “as is” without warranty of any kind, either express or implied, including without limitation, any warranties of merchantability, fitness for a particular purpose, and non-infringement. [[Lo-tech Systems Limited]] disclaims all responsibility for the accuracy or reliability of the software, hardware, and documentation and does not warrant they will meet licensee’s requirements, be uninterrupted or error-free, or that any defects in the software will be corrected. The entire risk arising out of use or performance of the software, hardware, and documentation provided under this agreement is assumed by the user. In no event shall [[Lo-tech Systems Limited]] (or its related companies) be liable for any incidental, special, indirect or consequential damages, lost profits or lost data, cost of procurement of substitute goods, technology or services, any claims by third parties (including but not limited to any defense thereof), any claims for indemnity or contribution, or other similar costs, whether asserted on the basis of contract, tort (including negligence), breach of warranty, or otherwise. In any event, [[Lo-tech Systems Limited]]'s liability under this agreement and for the software, hardware, and documentation is limited to the amount licensee paid to [[Lo-tech Systems Limited]] for the software, hardware, and/or documentation.

==Online Sales ==

The Terms and Conditions applied to online sales made via '''Lo-tech.co.uk''' are as follows.

=== Physical Items ===
#In this document the following words shall have the following meanings:
##“The Purchaser” means the legal entity who buys The Goods and whose details are registered with PayPal.
##“The Goods” means the articles listed in the order received by The Seller from PayPal for which physical order fulfillment is provided.
##“The Seller” and means Lo-tech Systems Limited.
# The order and these Terms and Conditions shall apply to The Goods only to the exclusion of all other terms and no variation to it can apply unless such variation is agreed in writing by The Seller. The Seller shall not be bound by any oral condition, warranty, guarantee or representation given or made unless the same is in writing, nor by any implied condition. All implied conditions and warranties whether as to quality, fitness or purpose or otherwise and whether arising by implication of law or to be implied from circumstances are hereby expressly excluded. The order shall not be binding upon The Seller unless or until specifically accepted by The Seller.
#All amounts are listed as and payable in UK pounds sterling. Payment is due at the time of order.
#Title to and property in The Goods shall not pass to The Purchaser until The Seller has been paid in full for The Goods.
#The Purchaser has certain rights in UK Law, including the right to return The Goods.
##Some products, such as unpopulated PCBs, are components and not complete products, and as such these can only be returned where in their original, as-shipped condition.
##Some products can be customised as part of the order process, and these goods are considered tailor-made or personalised for the purposes of the Consumer Contracts Regulations and acceptance of the order by The Seller is therefore final. As such The Purchaser will accept The Goods without any right to return The Goods except to the extent permitted by The Purchaser’s statutory rights or as provided for herein.
##The Purchaser must notify The Seller in writing by email of any intention to return goods for any reason.
## Except where returns are made due to breach of warranty (as defined below):
###The Purchaser is responsible for return postage costs; and
###The Purchaser assumes all responsibility for and hereby indemnifies The Seller against all import duties, taxes, customs fees, and all other third party charges arising.
#The Purchaser assumes all responsibility for any compliance related issues in the use of or performance of or decommissioning of The Goods, such as (but not limited to) electromagnetic radiation and environmental disposal costs.
#The Purchaser warrants to the Seller that:
##They agree to be bound by these Terms and Conditions and;
##The Goods will not be used, either directly or via any third party to which they are knowingly re-sold, in any way that could change the classification of The Goods in the context of the UK Strategic Export Control Lists (including but not limited to the Dual-Use Lists);
##The Goods will not be shipped onto any Country or location to which the sale would have been restricted due to trade embargo or similar restrictions; and
#The Seller provides the following as sole and exclusive warranty with The Goods:
##The Goods will be, on arrival, as described and function as described in documentation made available to the Purchaser prior to order;
##Product specific warranties as stated in the [[Compliance]] information for the particular product or product class at time of order;
##Any defects under these warranties must be notified in writing with 30 days of receipt.
#The Seller does not accept waste electrical items and is not a registered waste carrier, and as such cannot accept the return of waste electrical items ([[WEEE]]). The Seller fulfils its legal [[WEEE]] requirements, when arising due to the provision of in-scope products, by financially supporting the national network of [[WEEE]] recycling centres established by local authorities, achieved through membership of the national Distributor Take-back scheme (DTS).
#Time of dispatch and/or delivery of the Goods shall not be deemed to be of the essence of the contract. The Seller shall endeavour to meet the dispatch and/or delivery estimates quoted to the Purchaser. The Seller does not guarantee such dates. The Seller shall not be liable for any claims or liabilities arising out of late delivery of The Goods.
# Risk in The Goods shall pass on delivery but The Seller shall not be liable in respect of any damage to or loss of The Goods in transit and The Purchaser assumes all responsibility for and hereby indemnifies The Seller against all import duties, taxes, customs fees, and all other third party charges arising on the delivery of The Goods, and thereafter in relation to those Goods.
#Any claims for damage in transit shall be notified to The Seller by The Purchaser within 30 days of receipt and settled by way of refund to The Purchaser of the unit price paid for each item affected, upon receipt by The Seller of such affected items.
#The Purchaser shall indemnify The Seller and its related companies against any claims, loss, damage or other liability or expense incurred (including legal costs on a full indemnity basis) arising directly or indirectly out of the state, condition or use of The Goods, or in any way arising out of having entered into this Agreement, including without limitation product liability claims, or claims arising out of the use, reproduction or distribution of products and any associated software, hardware, documentation, and parts thereof (except in the case of death or personal injury caused by the Seller’s negligence).
#The Goods are not fault tolerant and are not designed, manufactured, or intended for use in control equipment in hazardous environments requiring fail-safe performance, such as industrial machinery, in which the failure of such components could lead to death or personal injury.
#The general and product specific [[Warnings]] provided must be observed both in the initial deployment and throughout the lifecycle of The Goods.
#Except in the case of death or personal injury caused by The Seller’s negligence, The Seller is not liable for any loss, injury or damage (including consequential or financial loss), due to any defect in The Goods.
#Except in the case of death or personal injury caused by The Seller’s negligence, under no circumstances will The Seller’s liability exceed the total of payments received by The Seller.
#If any term or provision of these Terms and Conditions is held invalid, illegal or unenforceable, in whole or in part for any reason by any Court, such part shall be deemed not to form part of the Terms and Conditions but the legality, validity or enforceability of the remainder of the Terms and Conditions shall not be affected.
#This sale of The Goods is considered to be executed in the United Kingdom and this Agreement shall be governed by and construed in accordance with the laws of England. Any dispute will be subject to the jurisdiction of the English Courts.

=== Downloads ===

#In this document the following words shall have the following meanings:
##“The Licensee” means the legal entity who buys a License to use The Downloads and whose details are registered with PayPal.
##"The Downloads" means the articles listed in the order received by The Licensor from PayPal for which digital order fulfillment is provided.
## "The Licensor" means Lo-tech Systems Limited.
# These license terms are an agreement between you and Lo-tech Systems Limited (or one of its affiliates). They apply to any items purchased with digital delivery through lo-tech.co.uk. IF YOU COMPLY WITH THESE LICENSE TERMS, YOU HAVE THE RIGHTS BELOW. BY ACCESSING THE DOWNLOADS, YOU ACCEPT THESE TERMS.
#USE RIGHTS. The Licensee grants The Licensor with continuous, non-expiring rights to use The Downloads for non-commercial purposes.
# DATA COLLECTION. The Downloads may contain unique identifiers that tie The Download to The Licensee via the sales order records.
# SCOPE OF LICENSE. The Downloads are licensed, not sold. Lo-tech Systems Limited reserves all other rights. Unless applicable law gives you more rights despite this limitation, you will not (and have no right to):
##Work around any technical limitations that allow use only in certain ways;
##Remove, minimize, block, or modify any notices or logos of Lo-tech Systems Limited, Lo-tech, Lo-tech.co.uk, or its suppliers;
##Use The Downloads in any way that is against the law or to create or propagate malware; or
##Share, publish, distribute, or lend The Downloads (except for any distributable code included therein), provide access to The Downloads for others to use, or transfer The Downloads or this agreement to any third party.
#EXPORT RESTRICTIONS. You must comply with all domestic and international export laws and regulations that apply to The Downloads, which include restrictions on destinations, end users, and end use.
# SUPPORT SERVICES. Lo-tech Systems Limited is not obligated under this agreement to provide any support services for The Downloads. Any support provided is “as is”, “with all faults”, and without warranty of any kind.
# Access to The Downloads is provided by email on receipt of payment. By accessing The Downloads, The Licensee consents to waiving of rights to the 14-day cooling-off period defined in the Distance Selling Regulations in exchange for immediate access.
#There is no right to return or refund except to the extent permitted by The Licensees statutory rights or as provided for herein.
# This sale of License for the use of The Downloads is considered to be executed in the United Kingdom and this Agreement shall be governed by and construed in accordance with the laws of England. Any dispute will be subject to the jurisdiction of the English Courts.
# The order shall not be binding upon The Licensee unless or until specifically accepted by The Licensee.
# All amounts are listed as and payable in UK pounds sterling (GBP). Payment is due at the time of order.
# Access to The Downloads will be provided by email within 72 hours of order and shall expire 72 hours after access has been granted.
# The general and product specific [[Warnings]] provided must be observed in the use of The Downloads.
#ENTIRE AGREEMENT. This agreement, and any other terms Lo-tech Systems Limited may provide for supplements, updates, or third-party components, is the entire agreement for The Downloads.
# DISCLAIMER OF WARRANTY. THE DOWNLOADS ARE LICENSED “AS IS.” THE LICENSEE BEARS THE RISK OF USING IT. Lo-tech Systems Limited GIVES NO EXPRESS WARRANTIES, GUARANTEES, OR CONDITIONS. TO THE EXTENT PERMITTED UNDER APPLICABLE LAWS, Lo-tech Systems Limited EXCLUDES ALL IMPLIED WARRANTIES, INCLUDING MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
# LIMITATION ON AND EXCLUSION OF DAMAGES:
## IF YOU HAVE ANY BASIS FOR RECOVERING DAMAGES DESPITE THE PRECEDING DISCLAIMER OF WARRANTY, YOU CAN RECOVER FROM Lo-tech Systems Limited ONLY DIRECT DAMAGES UP TO GBP £5.00. YOU CANNOT RECOVER ANY OTHER DAMAGES, INCLUDING CONSEQUENTIAL, LOST PROFITS, SPECIAL, INDIRECT, OR INCIDENTAL DAMAGES.
## This limitation applies to (a) anything related to The Downloads; and (b) claims for breach of contract, warranty, guarantee, or condition; strict liability, negligence, or other tort; or any other claim; in each case to the extent permitted by applicable law.
## It also applies even if Lo-tech Systems Limited knew or should have known about the possibility of the damages. The above limitation or exclusion may not apply to you because your state, province, or country may not allow the exclusion or limitation of incidental, consequential, or other damages.

==See Also==

*[[About]]
*[[Copyrights]]
*[[Warnings]]
*[[Compliance]]

Lo-tech Systems Limited

2026-01-24T19:56:07Z

James: Redirected page to About

#REDIRECT [[About]]

Compliance

2026-01-24T19:55:16Z

James: Updated to reflect change of company name.

== Unpopulated PCBs ==

'''lo-tech.co.uk''' un-populated PCBs are intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, or EVALUATION PURPOSES ONLY and are not considered by [[lo-tech.co.uk:About|Lo-tech Systems Limited]] to be finished end-products fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards.

These products do not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling ([[WEEE]]), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives, unless otherwise stated.

Should an un-populated PCB not meet the specifications provided on this site, the board may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies [[lo-tech.co.uk:About|Lo-tech Systems Limited]] from all claims arising from the handling or use of the goods. Due to the open construction of the products once assembled, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

== Digital Downloads ==
'''lo-tech.co.uk''' digitally delivered products (i.e. [[Terms and Conditions#Downloads|downloads]]) are intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, or EVALUATION PURPOSES ONLY and are not considered by [[lo-tech.co.uk:About|Lo-tech Systems Limited]] to be or to be used to create finished products fit for general consumer use. Persons making licensed use of these product(s) must have electronics training and observe good engineering practice standards. As such, the designs provided within these products are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards.

These products do not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling ([[WEEE]]), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives, unless otherwise stated. It is the Licensee's responsibility to ensure compliance with all local requirements accordingly.

== Lo-tech GPIO Interface Board rev.2 (Assembled Version) ==

The [[Lo-tech GPIO Interface Board rev.2]] (Assembled Version) complies with the relevant provisions of the RoHS Directive for the European Union. In common with all Electrical and Electronic Equipment (EEE) the device should not be disposed of as household waste (see [[WEEE]]). Alternative arrangements may apply in other jurisdictions.

=== Electromagnetic Compatibility (EMC) ===

''Note: EMC Performance of the Raspberry Pi is influenced greatly by the attached power supply and casing design. A properly grounded enclosure and a compliant power supply must be used with this product in order to meet FCC emission limits.''

; European Compliance Statement : This product is in conformity with the protection requirements of EU Council Directive 2004/108/EC on the approximation of the laws of the Member States relating to electromagnetic compatibility. This product has been tested and found to comply with the limits for Class B Information Technology Equipment according to the European Standard.

; Federal Communications Commission (FCC) Emissions Compliance Statement : Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the product documentation, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense. PLo-tech Systems Limited is not responsible for any radio or television interference caused by operating device under conditions other than recommended or by unauthorised changes or modifications to this equipment. Unauthorised changes or modifications could void the user's authority to operate the equipment. This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Responsible Party: [[Lo-tech Systems Limited]]

== Lo-tech Raspberry Pi VGA Interface (Assembled Version) ==

The [[Lo-tech RPi VGA Adapter]] (Assembled Version) complies with the relevant provisions of the RoHS Directive for the European Union. In common with all Electrical and Electronic Equipment (EEE) the device should not be disposed of as household waste (see [[WEEE]]). Alternative arrangements may apply in other jurisdictions.

=== Electromagnetic Compatibility (EMC) ===

''Note: EMC Performance of the Raspberry Pi is influenced greatly by the attached power supply and casing design. A compliant power supply must be used with this product in order to meet FCC emission limits.''

; European Compliance Statement : This product is in conformity with the protection requirements of EU Council Directive 2004/108/EC on the approximation of the laws of the Member States relating to electromagnetic compatibility. This product has been tested and found to comply with the limits for Class B Information Technology Equipment according to the European Standard.

; Federal Communications Commission (FCC) Emissions Compliance Statement : Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the product documentation, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense. Lo-tech Systems Limited is not responsible for any radio or television interference caused by operating device under conditions other than recommended or by unauthorised changes or modifications to this equipment. Unauthorised changes or modifications could void the user's authority to operate the equipment. This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Responsible Party: [[Lo-tech Systems Limited]]

== See Also ==

*[[lo-tech.co.uk:General_disclaimer|Terms and Conditions]]
*[[WEEE]]

Copyrights

2026-01-24T19:46:36Z

James: /* Lo-tech Brand and Logo */ Updated to reflect change of company name

== Lo-tech Brand and Logo ==

[[File:Lotech-logo-thumbnail-r01.png|thumb|right|Lo-tech Brand Logo]]
The words "Lo-tech" and "Lo-tech.co.uk" and the Lo-tech logo (right) are collectively the '''Lo-tech''' Brand Identifiers. '''Lo-tech''' is a trading name of [[lo-tech.co.uk:About|Lo-tech Systems Limited]].

The brand identifiers may only be used:

#to refer to or describe genuine '''Lo-tech''' products or services; or
#to state or indicate that another product is compatible with, works with, or can be used with, '''Lo-tech''' products.

When used in this way on a website, these should link to http://www.lo-tech.co.uk/

These brand identifiers may not be used:

#as part of a company name, company logo or product name;
#as part of a domain name;
#in a way that creates a false impression that a product or business is endorsed by, sponsored by, or associated with '''Lo-tech''';
#in a way that shows '''Lo-tech''', [[lo-tech.co.uk:About|Lo-tech Systems Limited]], or its products or services in a false or derogatory light;
#in connection with fake or counterfeit products;
#in a way that will damage our goodwill in any way.

== Third Party Materials ==

In general, information provided on this website is of historic interest and in some cases includes third-party supporting documentation and software for the express purpose of the preservation of associated hardware that is dependent on that documentation and software.

In some cases the original copyright owner is defunct, whilst in other cases there is no commercial reason for the original copyright holder to make such documentation and software available, but it should be noted that those third parties retain the copyright in such materials regardless, and that their permission may be required to use those materials.

== See Also ==

*[[About]]
*[[Terms and Conditions]]

About

2026-01-24T19:45:33Z

James: /* Legal bits */ Updated to reflect change of company name.

'''lo-tech.co.uk is home to a range of retro computing and RaspberryPi projects.'''

lo-tech has been developing assemble-yourself expansion boards for retro IBM and retro Tandy PCs since 2012, the range currently consisting of memory boards, storage boards, sound boards, and some diagnostics related products. The lo-tech product range as covers Raspberry Pi modules with a GPIO interface module, 24-bit VGA adapter, and an interface to Rollertec garage door controllers.

In additional to downloadable designs, Lo-tech boards are available through our authorised distributor, [https://texelec.com/product-tag/lo-tech/ TexElec].

If you have an idea for a Lo-tech PCB, please [https://www.lo-tech.co.uk/get-in-touch/ Get In Touch]!

== Legal bits ==

*Lo-tech and Lo-tech.co.uk are trading names of Lo-tech Systems Limited.
*Lo-tech Systems Limited is registered in England and Wales, company registration number 06648822.
*Hardware and software are provided under [[Terms and Conditions|a simple license]].

== See Also ==

*[[Copyrights]]
*[[Terms and Conditions]]
*[[Privacy policy]]

Lo-tech 2MB EMS Board

2025-08-31T09:02:43Z

James: Added narrative about how XMS words from https://mateusz.fr/exms86/

[[File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg|right|300px|Lo-tech 2MB EMS Board (r02), Assembled]]
The [[Lo-tech 2MB EMS Board]] is an 8-bit ISA expansion card providing up to 2MB of EMS for [[IBM Personal Computer 5150|IBM compatible PCs]]. The small form factor makes the board suitable for the [[IBM Portable Computer 5155]].

'''This board can now provide XMS for XT class machines''' using [https://mateusz.fr/exms86/ EXMS86, a TSR that provides XMS 2.0 memory services by leveraging an EMS 3.2 source written by Mateusz Viste]. With the authors kind permission, v0.9.7 is also available for download here as [https://lo-tech.co.uk/downloads/exms86/exms86-0.9.7.zip Binaries] and [https://www.lo-tech.co.uk/downloads/exms86/exms86-0.9.7-source.zip Source].

To purchase this board, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

Revision History:

*R01 - Prototype. See [[Lo-tech 2MB EMS Board (prototype) Resources]].
*R02 - First production release.

== Technical Description ==

The [[Lo-tech 2MB EMS Board]] utilises up to four [{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM chips] to provide up to 16Mb (=2MB) total RAM capacity, buffered via a 74ACT245 to ensure compatibility with TTL logic levels, on an 8-bit ISA expansion card. For applications that support EMS, this provides a way to install more than the 1MB total address capacity of the 8086 and 8088 processors.

Following the LIM EMS specification, physical RAM is divided into 16KB pages and addressed via a single 64KB window (the 'page frame') in the [http://en.wikipedia.org/wiki/Upper_memory_area upper memory]. The pages presented within the window are determined by the value set in four page registers, which are programmed through IO ports. A jumper block enables the page frame IO port base addresses to configured to match the system requirements.

For operation, the EMS board requires a LIM memory manager driver, [[LTEMM.EXE]]. This driver provides LIM 4 compatibility.

== XMS Capability ==
The following is included with the kind permission of Mateusz Viste.

''It is a common misconception that XMS is only possible on 386+ machines. XMS (v2.0) is fundamentally a memory-copying API. Applications using XMS do not care where the memory comes from. While XMS is commonly associated with RAM located above the 1 MB boundary (often called "extended memory") on 386+ PCs, that's a historical convention, not a technical requirement. Hence it is perfectly possible for a driver to expose memory via the XMS API even if said memory is not part of the system's RAM - like memory from an EMS board.''

Source: [https://mateusz.fr/exms86/ EXMS86 (EMS-backed XMS)]

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:2MB-EMS-Board-r02-schematic.png
File:2MB-EMS-Board-r02-front.png
File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2014 Peacon Ltd.

=== Assembly ===

This PCB makes use of SMT components:

*SOIC chips have a pitch of 1.27mm
*0603 package capacitors and resistors

Assembly requires flux and a temperature controlled soldering station.

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C15 || 0.1uF || X7R Ceramic Capacitor || 0603 || 15 || 1414610 || 80-C0603C104K4R
|-
|C16 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || 140-REA100M1CBK0511P
|-
|IC1, IC5 || - || 74HCT688DW || SOIC-20 || 2 || 1085321 || 771-HCT688D652 or 595-CD74HCT688M
|-
|IC2 || - || 74HCT139D || SOIC-16 || 1 || 1085308 || 771-74HCT139D-T
|-
|IC3 || - || 74HCT04D || SOIC-14 || 1 || 1085299 || 595-SN74HCT04D
|-
|IC4 || - || 74HCT32D || SOIC-14 || 1 || 1201305 || 771-74HCT32D-T
|-
|IC6..IC9 || - || 74HCT573D || SOIC-20 || 4 || 1201309 || 771-74HCT573D
|-
|IC10 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || 771-74HCT245D
|-
|IC11 || - || 74HCT138D || SOIC-16 || 1 || 1201307 || 771-74HCT138D-T
|-
|IC12..IC15 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 4 || 1562901 || 913-AS6C4008-55SIN
|-
|JP1 || - || PINHD-2X4 || - || 1 || 1593441 || 649-77313-101-08LF
|-
|RN1..RN3 || 10k || RESISTOR, ARRAY-4, 10K, 1206 || 1206 || 3 || 1770137 || 652-CAY16-103J4LF
|}

Note: Only one SRAM chip is required to build a functioning board (populate SRAM chips in order from IC12).

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_3|Lo-tech ISA Slot Bracket Type 3]].

== JP1: Board Configuration ==

The board is configured via four jumpers on the pin-header JP1 (O=open, C=closed, position 1 is furthest from IC11 (74LS138D)):

{| class="wikitable"
!Page Frame Base Address !!IO Port Base Address
|-
|
{| class="wikitable"
!Value (1,2) !!Base Address
|-
| C,C || C000h
|-
| O,C || D000h
|-
| C,O || E000h
|-
| O,O || (invalid)
|}
|
{| class="wikitable"
!Value (3,4) !!Base Address
|-
| C,C || 260-263h
|-
| O,C || 264-267h
|-
| C,O || 268-26Bh
|-
| O,O || 26C-26Fh
|}
|-
|}

*The recommended configuration is E000h and 260h, being C,O,C,C.
*The [{{SERVER}}/downloads/2MB-EMS-Board/testems.zip Lo-tech EMS Board Test Utility] can assist with hardware testing after build.

== See Also ==

*[[Lo-tech Memory Boards]]
*[[Lo-tech Memory Board FAQ]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech 2MB EMS Board

2025-08-31T08:02:50Z

James: Corrected link

[[File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg|right|300px|Lo-tech 2MB EMS Board (r02), Assembled]]
The [[Lo-tech 2MB EMS Board]] is an 8-bit ISA expansion card providing up to 2MB of EMS for [[IBM Personal Computer 5150|IBM compatible PCs]]. The small form factor makes the board suitable for the [[IBM Portable Computer 5155]].

'''This board can now provide XMS for XT class machines''' using [https://mateusz.fr/exms86/ EXMS86, a TSR that provides XMS 2.0 memory services by leveraging an EMS 3.2 source written by Mateusz Viste]. With the authors kind permission, v0.9.7 is also available for download here as [https://lo-tech.co.uk/downloads/exms86/exms86-0.9.7.zip Binaries] and [https://www.lo-tech.co.uk/downloads/exms86/exms86-0.9.7-source.zip Source].

To purchase this board, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

Revision History:

*R01 - Prototype. See [[Lo-tech 2MB EMS Board (prototype) Resources]].
*R02 - First production release.

== Technical Description ==

The [[Lo-tech 2MB EMS Board]] utilises up to four [{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM chips] to provide up to 16Mb (=2MB) total RAM capacity, buffered via a 74ACT245 to ensure compatibility with TTL logic levels, on an 8-bit ISA expansion card. For applications that support EMS, this provides a way to install more than the 1MB total address capacity of the 8086 and 8088 processors.

Following the LIM EMS specification, physical RAM is divided into 16KB pages and addressed via a single 64KB window (the 'page frame') in the [http://en.wikipedia.org/wiki/Upper_memory_area upper memory]. The pages presented within the window are determined by the value set in four page registers, which are programmed through IO ports. A jumper block enables the page frame IO port base addresses to configured to match the system requirements.

For operation, the EMS board requires a LIM memory manager driver, [[LTEMM.EXE]]. This driver provides LIM 4 compatibility.

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:2MB-EMS-Board-r02-schematic.png
File:2MB-EMS-Board-r02-front.png
File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2014 Peacon Ltd.

=== Assembly ===

This PCB makes use of SMT components:

*SOIC chips have a pitch of 1.27mm
*0603 package capacitors and resistors

Assembly requires flux and a temperature controlled soldering station.

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C15 || 0.1uF || X7R Ceramic Capacitor || 0603 || 15 || 1414610 || 80-C0603C104K4R
|-
|C16 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || 140-REA100M1CBK0511P
|-
|IC1, IC5 || - || 74HCT688DW || SOIC-20 || 2 || 1085321 || 771-HCT688D652 or 595-CD74HCT688M
|-
|IC2 || - || 74HCT139D || SOIC-16 || 1 || 1085308 || 771-74HCT139D-T
|-
|IC3 || - || 74HCT04D || SOIC-14 || 1 || 1085299 || 595-SN74HCT04D
|-
|IC4 || - || 74HCT32D || SOIC-14 || 1 || 1201305 || 771-74HCT32D-T
|-
|IC6..IC9 || - || 74HCT573D || SOIC-20 || 4 || 1201309 || 771-74HCT573D
|-
|IC10 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || 771-74HCT245D
|-
|IC11 || - || 74HCT138D || SOIC-16 || 1 || 1201307 || 771-74HCT138D-T
|-
|IC12..IC15 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 4 || 1562901 || 913-AS6C4008-55SIN
|-
|JP1 || - || PINHD-2X4 || - || 1 || 1593441 || 649-77313-101-08LF
|-
|RN1..RN3 || 10k || RESISTOR, ARRAY-4, 10K, 1206 || 1206 || 3 || 1770137 || 652-CAY16-103J4LF
|}

Note: Only one SRAM chip is required to build a functioning board (populate SRAM chips in order from IC12).

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_3|Lo-tech ISA Slot Bracket Type 3]].

== JP1: Board Configuration ==

The board is configured via four jumpers on the pin-header JP1 (O=open, C=closed, position 1 is furthest from IC11 (74LS138D)):

{| class="wikitable"
!Page Frame Base Address !!IO Port Base Address
|-
|
{| class="wikitable"
!Value (1,2) !!Base Address
|-
| C,C || C000h
|-
| O,C || D000h
|-
| C,O || E000h
|-
| O,O || (invalid)
|}
|
{| class="wikitable"
!Value (3,4) !!Base Address
|-
| C,C || 260-263h
|-
| O,C || 264-267h
|-
| C,O || 268-26Bh
|-
| O,O || 26C-26Fh
|}
|-
|}

*The recommended configuration is E000h and 260h, being C,O,C,C.
*The [{{SERVER}}/downloads/2MB-EMS-Board/testems.zip Lo-tech EMS Board Test Utility] can assist with hardware testing after build.

== See Also ==

*[[Lo-tech Memory Boards]]
*[[Lo-tech Memory Board FAQ]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech 2MB EMS Board

2025-08-31T08:02:03Z

James: Added EXMS86 info and download links

[[File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg|right|300px|Lo-tech 2MB EMS Board (r02), Assembled]]
The [[Lo-tech 2MB EMS Board]] is an 8-bit ISA expansion card providing up to 2MB of EMS for [[IBM Personal Computer 5150|IBM compatible PCs]]. The small form factor makes the board suitable for the [[IBM Portable Computer 5155]].

'''This board can now provide XMS for XT class machines''' using [https://mateusz.fr/exms86/ EXMS86, a TSR that provides XMS 2.0 memory services by leveraging an EMS 3.2 source written by Mateusz Viste]. With the authors kind permission, v0.9.7 is also available for download here as [http://lo-tech.co.uk/downloads/exms86/exms86-0.9.7.zip Binaries] and [https://www.lo-tech.co.uk/downloads/exms86/exms86-0.9.7-source.zip Source].

To purchase this board, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

Revision History:

*R01 - Prototype. See [[Lo-tech 2MB EMS Board (prototype) Resources]].
*R02 - First production release.

== Technical Description ==

The [[Lo-tech 2MB EMS Board]] utilises up to four [{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM chips] to provide up to 16Mb (=2MB) total RAM capacity, buffered via a 74ACT245 to ensure compatibility with TTL logic levels, on an 8-bit ISA expansion card. For applications that support EMS, this provides a way to install more than the 1MB total address capacity of the 8086 and 8088 processors.

Following the LIM EMS specification, physical RAM is divided into 16KB pages and addressed via a single 64KB window (the 'page frame') in the [http://en.wikipedia.org/wiki/Upper_memory_area upper memory]. The pages presented within the window are determined by the value set in four page registers, which are programmed through IO ports. A jumper block enables the page frame IO port base addresses to configured to match the system requirements.

For operation, the EMS board requires a LIM memory manager driver, [[LTEMM.EXE]]. This driver provides LIM 4 compatibility.

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:2MB-EMS-Board-r02-schematic.png
File:2MB-EMS-Board-r02-front.png
File:Lo-tech-2MB-EMS-Board-assembled-r02.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2014 Peacon Ltd.

=== Assembly ===

This PCB makes use of SMT components:

*SOIC chips have a pitch of 1.27mm
*0603 package capacitors and resistors

Assembly requires flux and a temperature controlled soldering station.

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C15 || 0.1uF || X7R Ceramic Capacitor || 0603 || 15 || 1414610 || 80-C0603C104K4R
|-
|C16 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || 140-REA100M1CBK0511P
|-
|IC1, IC5 || - || 74HCT688DW || SOIC-20 || 2 || 1085321 || 771-HCT688D652 or 595-CD74HCT688M
|-
|IC2 || - || 74HCT139D || SOIC-16 || 1 || 1085308 || 771-74HCT139D-T
|-
|IC3 || - || 74HCT04D || SOIC-14 || 1 || 1085299 || 595-SN74HCT04D
|-
|IC4 || - || 74HCT32D || SOIC-14 || 1 || 1201305 || 771-74HCT32D-T
|-
|IC6..IC9 || - || 74HCT573D || SOIC-20 || 4 || 1201309 || 771-74HCT573D
|-
|IC10 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || 771-74HCT245D
|-
|IC11 || - || 74HCT138D || SOIC-16 || 1 || 1201307 || 771-74HCT138D-T
|-
|IC12..IC15 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 4 || 1562901 || 913-AS6C4008-55SIN
|-
|JP1 || - || PINHD-2X4 || - || 1 || 1593441 || 649-77313-101-08LF
|-
|RN1..RN3 || 10k || RESISTOR, ARRAY-4, 10K, 1206 || 1206 || 3 || 1770137 || 652-CAY16-103J4LF
|}

Note: Only one SRAM chip is required to build a functioning board (populate SRAM chips in order from IC12).

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_3|Lo-tech ISA Slot Bracket Type 3]].

== JP1: Board Configuration ==

The board is configured via four jumpers on the pin-header JP1 (O=open, C=closed, position 1 is furthest from IC11 (74LS138D)):

{| class="wikitable"
!Page Frame Base Address !!IO Port Base Address
|-
|
{| class="wikitable"
!Value (1,2) !!Base Address
|-
| C,C || C000h
|-
| O,C || D000h
|-
| C,O || E000h
|-
| O,O || (invalid)
|}
|
{| class="wikitable"
!Value (3,4) !!Base Address
|-
| C,C || 260-263h
|-
| O,C || 264-267h
|-
| C,O || 268-26Bh
|-
| O,O || 26C-26Fh
|}
|-
|}

*The recommended configuration is E000h and 260h, being C,O,C,C.
*The [{{SERVER}}/downloads/2MB-EMS-Board/testems.zip Lo-tech EMS Board Test Utility] can assist with hardware testing after build.

== See Also ==

*[[Lo-tech Memory Boards]]
*[[Lo-tech Memory Board FAQ]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech XT-CF flash utility

2024-08-26T20:11:29Z

James:

The Lo-tech XT-CF flash utility is a simple DOS program that writes a binary input file to the ROM on the [[Lo-tech XT-CF Boards]] and [[Lo-tech 8-bit ROM Board]], both of which use ST39SF0x0 or AMIC A29010 flash chips.

== Usage ==

flash [image-file] [base-address]

where:

*<tt>[image-file]</tt> is the name of the binary file to load
*<tt>[base-address]</tt> is the base address of the chip, for example <tt>D000</tt>

Since the boards have 32 or 64KB available, multiple ROM binaries can be written out by appending them into a single file ensuring images are 2KB aligned; however note that the entire flash chip is erased before programming.

== Sample Output ==

C:\>flash
Lo-tech XT-CF and 8-bit ROM Board Flash Programmer, version 1.4
Supports SST 29xE010/39SF0x0, and AMIC A29010 flash chips.

Usage:

Write an image file to the ROM. The ROM is completely
erased, then the file copied. Can be used with ROMs
between 2KB and 64KB. Note: Checksum is not calculated.

eg: flash [image-file] [base-address]

[image-file] - ROM image
[base-address] - hex ROM window base address, i.e. D000
must be A000-F800

== Downloads ==

*[{{SERVER}}/downloads/XT-IDE/lo-tech-Flash-utility.zip Flash utility executable and source (ZIP file)]

== See Also ==

*[[Lo-tech XT-CF flash utility source]]
*[[Lo-tech 8-bit ROM Board]]
*[[Lo-tech XT-CF Boards]]

Lo-tech XT-CF flash utility

2024-08-26T20:09:58Z

James: Updated sample output to reflect version 1.4

The Lo-tech XT-CF flash utility is a simple DOS program that writes a binary input file to the ROM on the [[Lo-tech XT-CF Boards]] and [[Lo-tech 8-bit ROM Board]], both of which use ST39SF0x0 or AMIC A29010 flash chips.

== Usage ==

flash [image-file] [base-address]

where:

*<tt>[image-file]</tt> is the name of the binary file to load
*<tt>[base-address]</tt> is the base address of the chip, for example <tt>D000</tt>

Since the boards have 32 or 64KB available, multiple ROM binaries can be written out by appending them into a single file ensuring images are 2KB aligned; however note that the entire flash chip is erased before programming.

== Sample Output ==

C:\>flash
Lo-tech XT-CF and 8-bit ROM Board Flash Programmer. Usage:

Write an image file to the ROM. The ROM is completely
erased, then the file copied. Can be used with ROMs
between 2KB and 64KB. Note: Checksum is not calculated.

eg: flash [image-file] [base-address]

[image-file] - ROM image
[base-address] - hex ROM window base address, i.e. D000
must be A000-F800

== Downloads ==

*[{{SERVER}}/downloads/XT-IDE/lo-tech-Flash-utility.zip Flash utility executable and source (ZIP file)]

== See Also ==

*[[Lo-tech XT-CF flash utility source]]
*[[Lo-tech 8-bit ROM Board]]
*[[Lo-tech XT-CF Boards]]

Lo-tech XT-CF flash utility source

2024-08-26T19:55:51Z

James: /* Code */ Updated to version 1.4 - resolves long-standing bug preventing programming of ROMs that are exactly 64KB

Source code for a simple [[lo-tech XT-CF flash utility]], which can be compiled using [[Turbo Pascal]] 6. Compiled code can be downloaded [{{SERVER}}/downloads/XT-IDE/lo-tech-Flash-utility.zip here].

== Code ==
<source lang="pascal">
Program Flash;

{
Simple utility to read or write ROM images to or from SST39SF or AMIC A29010
flash chips, as used by the lo-tech XT-CF and Universal ROM Boards.

See http://www.lo-tech.co.uk/wiki/XT-CF-Boards

Written by: James Pearce
Last Updated: 01-Aug-24

VERSION HISTORY:

0.1 - Initial beta
0.2 - Added custom delay routines, to make it work on Pentium and higher
0.3 - Corrected maximum delay loop setting
1.0 - Initial 'finished' release for Peacon XT-CF board:
- removed ROM size parameter (as ROM is hard-wired to be 32KB)
1.1 - Updated release to support Peacon 8-Bit ROM Board:
- Included prompt to confirm writing
- Added (back) ROMSIZE parameter, as it could be 32 or 64KB
- Added ability to merge code
1.2 - Rebranded to lo-tech
Added support for AMIC A29010A 1Mb flash chip
ROMSIZE parameter removed (again) as not needed; just use an image > 32K
1.3 - Added support for SST29EE010 and SST29LE010 flash chips
Corrected usDelayLoop (was calibrated at 500uS instead of 125uS)
1.4 - Corrected bug writing 64K ROMs; removed interactive mode placeholder

COMMAND LINE USAGE:

flash [image-file] [chip-base-address]

Examples:

1. To overwrite the entire chip whose base address is D000, with the
contents of an image file of between 2KB and 64KB:

flash xtide.bin D000

In all cases, the ROM is completely erased and reprogrammed, regardless
of the size of the image file.
}

uses dos, crt;

CONST
FLASH_OK : BOOLEAN = TRUE;
FLASH_ERROR : BOOLEAN = FALSE;
RES_OK : Byte = 0;
RES_UNDER : Byte = 1;
RES_OVER : Byte = 2;
VERSION : String = '1.4';

CHIP_UNKNOWN : String = 'Unknown';
SST29EE010 : String = 'SST 29EE010';
SST29LE010 : String = 'SST 29LE010';
SST512Kb : String = 'SST 512Kb';
SST1Mb : String = 'SST 1Mb';
SST2Mb : String = 'SST 2Mb';
SST4Mb : String = 'SST 4Mb';
AMIC1Mb : String = 'AMIC A29010';

TYPE
PByte = ^BYTE;

VAR
{global variables for the delay routines}
DelayCounter : LongInt;
Hr, Mn,
Sec, S100 : Word;

{global variables recording chip type}
ChipType : String;

procedure start_clock;
{stores the current system clock time in static globals, which
can then be used as a time base by function stop_clock at some
later point}
begin
GetTime(Hr,Mn,Sec,S100);
end;

function stop_clock : longint;
{returns number of miliseconds since start_clock was called,
assuming the day remains the same that is}
var h, m, s, cs : word;
begin
GetTime(h,m,s,cs);
stop_clock := ((h*3600000)+(m*60000)+(s*1000)+(cs*10)) -
((Hr*3600000)+(Mn*60000)+(Sec*1000)+(S100*10));
end;{function stop_clock}

procedure delayLoop( ms : word );
{creates a delay of ms miliseconds (once calibrated) by running
some DIV instructions}
var
a, b, c : word;
x : word;
y : LongInt;

begin
{first check if the in-built delay can be used}
if DelayCounter < 1 then Delay(ms)
else begin
c := WORD(DelayCounter AND $FFFF);
for x := 1 to ms do
begin
for y := 1 to DelayCounter do
begin
a := b div c;
inc(b);
end;{for}
end;{for x}
end;{if/else}
end;{procedure}

procedure usdelayLoop( count : word );
{creates a delay of count x 125 microseconds (once calibrated) by running
some DIV instructions}
var
a, b, c : word;
x : word;
y, ShortWait : LongInt;

begin
c := WORD(DelayCounter AND $FFFF);
ShortWait := DelayCounter SHR 3; {ms to 125us}
for x := 1 to count do
begin
for y := 1 to ShortWait do
begin
a := b div c;
inc(b);
end;{for}
end;{for x}
end;{procedure}

function test_delay : byte;
var
interval : longint;

begin
start_clock;
delayLoop(110); {testing for 110ms delay}
interval := stop_clock;
if interval < 110 then test_delay := RES_UNDER
else if interval > 110 then test_delay := RES_OVER
else test_delay := RES_OK;
end;{function test_delay}

procedure calibrate_delay;
var
res : byte;
interval : LongInt;

begin
{first check if the in-built delay procedure can be used. Otherwise
an XT will take a long time calibrating, for no purpose}
start_clock;
delayLoop(110); {testing for 110ms delay}
interval := stop_clock;
{ if interval = 110 then
DelayCounter := -1 {built-in procedure will be used}
{ else}
begin
{calibration required.}
{div is c.80 clocks on an 8088 => ~60 divs per ms}
DelayCounter := 30;
res := RES_UNDER;
while res <> RES_OK do
begin
res := test_delay;
if DelayCounter >= $40000000 then
begin
{we can't calibrate properly as we're about to overflow}
RES := RES_OK; {end the loop}
DelayCounter := $7FFFFFFF; {maximum value as it's signed}
end else
begin
if res = RES_UNDER then DelayCounter := DelayCounter * 2; {we need more delay}
if res = RES_OVER then DelayCounter := DelayCounter * 2 div 3; {we've overshot}
end;{if/else}
end;{while}
end;{if interval/else}
end;{procedure calibrate_delay}

function HexToWord( s : string ) : word;
{converts the hex represented by the string, to a WORD}
var
i : Byte;
Wd : Word;
Digit : Byte;
Error : Boolean;
begin
Wd := 0; Error := False;
if (length(s) <= 4) then begin
for i := 1 to length(s) do begin
case s[i] of
'0'..'9' : Digit := BYTE(s[i]) - 48;
'A'..'F' : Digit := 10 + (BYTE(s[i]) - 65);
'a'..'f' : Digit := 10 + (BYTE(s[i]) - 97);
else Error := True;
end;{case}
if Error then i := length(s)
else Wd := (Wd SHL 4) + Digit;
end;{for}
end;{if}
if Error then HexToWord := 0
else HexToWord := Wd;
end;{function HexToWord}

function WordToHex( Wd : word ) : string;
{converts a word to ASCII hex}
var
Digit, i : Byte;
AsciiDigit : Char;
s : string;
begin
BYTE(s[0]) := 4; {set string length}
for i := 4 downto 1 do
begin
{get the low 4 bits of Wd to Digit, and SHR Wd 4}
asm
mov ax, Wd
mov bx, ax
and bl, $0F
cmp bl, 10
jb @ZeroToNine
add bl, 17
@ZeroToNine:
add bl, 48
mov AsciiDigit, bl
shr ax, 1
shr ax, 1
shr ax, 1
shr ax, 1
mov Wd, ax
end;{asm}
s[i] := AsciiDigit;
end;{for i}
WordToHex := s;
end;{function WordToHex}

function Caps( s : string ) : string;
{returns string capitalised}
var
i : byte;
tempstr : string;

begin
BYTE(TempStr[0]) := BYTE(s[0]); {set length}
for i := 1 to 255 do
TempStr[i] := UpCase(s[i]); {copy all chars}
Caps := TempStr;
end;{function Caps}

function FlashType( baseaddr : word ) : Boolean;
{Attempts to determine flash chip type from supported types.
Returns FLASH_OK if determined properly, FLASH_ERROR otherwise.
Result itself is stored in global variable ChipType}
var
Location : ^byte;

begin
ChipType := CHIP_UNKNOWN;

{First check for SST39SF chips}
{ChipID routine entry...}
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $90;

{check what's there}
{v1.3 - added 125uS delay, required by SST29EE010 before polling chip ID}
usdelayLoop(1);

Location := ptr( baseaddr, 0 );
If Location^ = $BF then
begin
Location := ptr( baseaddr, 1 );
case Location^ of
$07 : ChipType := SST29EE010;
$08 : ChipType := SST29LE010;
$B4 : ChipType := SST512Kb;
$B5 : ChipType := SST1Mb;
$B6 : ChipType := SST2Mb;
$B7 : ChipType := SST4Mb;
end; {case}
{Exit ChipID routine...}
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $F0;
usdelayLoop(1); {125uS delay; required by SST29EE010}
end {if SST chip detected}
else
begin
{SST not detected; check now for AMIC A29010}
{Autoselect mode routine entry...}
Location := ptr( baseaddr, $555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AA );
Location^ := $55;
Location := ptr( baseaddr, $555 );
Location^ := $90;

{check what's there}
Location := ptr( baseaddr, 0 );
If Location^ = $37 then
begin
Location := ptr( baseaddr, 1 );
case Location^ of
$A4 : ChipType := AMIC1Mb;
end;{case}
{Exit Autoselect mode by issuing reset...}
Location^ := $F0;
end;{if AMIC chip detected}
end;{if/else}

{return result}
If ChipType = CHIP_UNKNOWN then
FlashType := FLASH_ERROR
else
FlashType := FLASH_OK;
end;{function FlashType}

function eraseChip( baseaddr : word ) : boolean;
{erases the entire chip; returns FLASH_OK if successful}
var
Location : ^byte;
DQ7 : Byte;
Done : Boolean;
Error : Boolean;
LoopCount,
LoopMax : Word;
DivRes : Byte;
lastToggle,
thisToggle : Byte;

begin
{Route depends on the chip type}
If (ChipType = AMIC1Mb) or (ChipType = CHIP_UNKNOWN) then
begin
{AMIC A29010 erase command sequence}
Location := ptr( baseaddr, $555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AA );
Location^ := $55;
Location := ptr( baseaddr, $555 );
Location^ := $80;
Location := ptr( baseaddr, $555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AA );
Location^ := $55;
Location := ptr( baseaddr, $555 );
Location^ := $10;
LoopMax := 1875; {set timeout to 75s (1875 x 40ms)}
end else begin
{SST39SF and SST29xx erase command code...}
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $80;
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $10;
LoopMax := 25; {set timeout to 1s (25 x 40ms)}
end;{Chip specific erase command entry select}

{then wait}
Done := False;
Error := False;
LoopCount := 0;
Location := ptr( baseaddr, 0 ); {we'll poll address 0 to check when done}

if (ChipType = SST29EE010) or (ChipType = SST29LE010) then
begin
usDelayLoop(2); {250uS delay before we can poll}
{SST29xE010 provides a busy toggle bit (DQ6) that must be polled}
lastToggle := Location^ AND $80; {get DQ6 from device}
while (not done) and (not error) do
begin
inc(LoopCount);
delayLoop(40); {40ms delay}
thisToggle := Location^ AND $80; {get DQ6 from device}
if (thisToggle = lastToggle) then Done := true;
lastToggle := thisToggle;
if LoopCount mod 100 = 0 then write('.'); {provide an indication things are still running}
if (LoopCount = LoopMax) or KeyPressed then Error := true; {trap timeout based on chip type}
end;{while}
if (Done) then begin
{erase seemed to succeed, so enable SDP}
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $A0;
end;{enable SDP}
end else begin
{other chips are handled with data polling}
while (not done) and (not error) do
begin
inc(LoopCount);
delayLoop(40); {40ms delay}
if Location^ = $FF then Done := true;
if LoopCount mod 100 = 0 then write('.'); {provide an indication things are still running}
if (LoopCount = LoopMax) or KeyPressed then Error := true; {trap timeout based on chip type}
end;{while}
end;{if/else}

If Error then
begin
If KeyPressed then write('Interrupted by keypress.')
else begin
WriteLn('** Timeout **');
Write('Expected FFh, but found ',WordToHex(Location^),'h.');
end;{else}
eraseChip := FLASH_ERROR;
end else eraseChip := FLASH_OK;
end;{function eraseChip}

function writeByte( baseaddr : word; offset : word; b : byte ) : BOOLEAN;
{writes byte b to baseaddr:offset, returns FLASH_OK if successful}
var
Location : ^byte;
DQ7 : Byte;
Done : Boolean;
Error : Boolean;
DivRes : byte;
usDelay,
LoopCount,
LoopMax : Word;

begin
{Routine depends on the chip type}
If (ChipType = AMIC1Mb) or (ChipType = CHIP_UNKNOWN) then
begin
{AMIC A29010 erase command sequence}
Location := ptr( baseaddr, $555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AA );
Location^ := $55;
Location := ptr( baseaddr, $555 );
Location^ := $A0;
Location := ptr( baseaddr, offset );
Location^ := b;
usDelay := 1; {1 = 125us delay per byte}
LoopMax := 3; {timeout after 375us (3x125)}
end else begin
{SST39SF byte program command sequence}
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $A0;
Location := ptr( baseaddr, offset );
Location^ := b;
usDelay := 1; {1 = 125us delay per byte}
LoopMax := 2; {timeout after 250us (2x125)}
end;{if/else}

{then wait}
Done := False;
Error := False;
LoopCount := 0;
while (not done) and (not error) do
begin
inc(LoopCount);
usdelayLoop(usDelay);
if Location^ = b then Done := true;
if (LoopCount = LoopMax) or KeyPressed then Error := true;
end;{while}

If Error then writeByte := FLASH_ERROR
else writeByte := FLASH_OK;
end;{function writeByte}

function writePage( baseaddr, pageaddr : word; var PageData : PByte ) : BOOLEAN;
{writes a 128 byte page to the device, returns FLASH_OK if successful}
{baseaddr = ROM chip base address
pageaddr = offset of page to be programmed (0, 128, 256...)
pagedata = pointer to 128 bytes of data to be programmed.}
var
Location : ^byte;
DQ7 : Byte;
Done : Boolean;
Error : Boolean;
DivRes : byte;
usDelay,
LoopCount,
LoopMax : Word;
i : byte;

begin
Error := True;
{Routine depends on the chip type}
if (ChipType = SST29EE010) or (ChipType = SST29LE010) then
begin
Location := ptr( baseaddr, 0 );
asm cli end; {clear interrupts - each bytes has to be sent within 100uS}
{SST29xE page SDP unlock sequence}
Location := ptr( baseaddr, $5555 );
Location^ := $AA;
Location := ptr( baseaddr, $2AAA );
Location^ := $55;
Location := ptr( baseaddr, $5555 );
Location^ := $A0;

{device should now (immediately) accept 128 bytes of data}
Location := ptr( baseaddr, pageaddr );
for i := 1 to 128 do
begin
Location^ := PageData^;
inc(Location);
inc(PageData);
end;{for}

{data sent to buffer - now wait for data to be ingested}
asm sti end; {re-enable interupts}
usdelayLoop(2); {250uS delay before we can check}

{then wait}
Done := False;
Error := False;
LoopCount := 0;
usDelay := 4; {4 = 500us delay per byte}
LoopMax := 20; {timeout after 10ms (20 x 500us)}

while (not done) and (not error) do
begin
inc(LoopCount);
usdelayLoop(usDelay);
if Location^ = PageData^ then Done := true;
if (LoopCount = LoopMax) or KeyPressed then Error := true;
end;{while}

end;{if/else}
If Error then writePage := FLASH_ERROR
else writePage := FLASH_OK;
end;{function writePage}

procedure FlashChip( imagefile, baseaddr : string );
{called once parameters are validated; this does the work!}
{$R- disable range checking, as the ROM is directly accessed and could be
64K exactly}
type
TRomImage = array[0..31767] of byte;

var
RomImage1,
RomImage2 : ^TRomImage;
Rom : ^TRomImage; {used to compare}
CurrentPage : PByte;
RomFile : File;
BytesRead : Longint;
BytesRead1,
BytesRead2,
CurrentPos : word;
Res : Integer;
RomBaseAddr : word;
Error : Boolean;
X, Y : Byte;
UpdateInt : word;
UpdateCount : word;
Percent : Byte;
Ch : Char;
CurrentByte : Byte;

begin
{load the ROM image file}
write('Opening ROM image... ');
new(RomImage1); new(RomImage2);
assign(RomFile,imagefile);
{$I- disable IO error checking}
reset(RomFile,1);
{$I+ }
if IOResult <> 0 then
begin
WriteLn('Unable to open file.');
Exit;
end;{if}
if (FileSize(RomFile) < 2048) or (FileSize(RomFile) > 65536) then
begin
{ROM file too small or too large}
WriteLn('ROM file must be between 2 and 64K.');
Close(RomFile);
Exit;
end else WriteLn('OK');

{get chip base address}
RomBaseAddr := HexToWord( baseaddr ); {starting location of ROM}

{Display detected flash type}
If FlashType(RomBaseAddr) = FLASH_OK then
WriteLn( 'Detected ', ChipType, ' Flash Chip at ', baseaddr, 'h' )
else
WriteLn( 'Unable to determine flash chip type. Attempting JDEC programming.');

{read the file}
Write('Reading... ');
BytesRead2 := 0;
BlockRead(RomFile,RomImage1^,32768,BytesRead1);
if not EoF(RomFile) then
BlockRead(RomFile,RomImage2^,32768,BytesRead2);
BytesRead := Longint(BytesRead1) + Longint(BytesRead2);
WriteLn( BytesRead, ' bytes read OK.');
Close(RomFile);

{erase the chip}
Write('Erasing ' );
if (eraseChip(RomBaseAddr) = FLASH_OK) then
begin
{erase was successful; write out new code}
writeLn('OK');
Error := False;

If BytesRead > 0 then
begin
WriteLn('Programming... ');
UpdateCount := 0;
Percent := 0;
X := WhereX;
Y := WhereY;
write( '0%' );

if (ChipType = SST29EE010) or (ChipType = SST29LE010) then
begin
{page-mode programming}
while CurrentPos < Pred(BytesRead) do
begin
if CurrentPos < 32768 then
CurrentPage := Addr(RomImage1^[CurrentPos])
else
CurrentPage := Addr(RomImage2^[CurrentPos-32768]);
if (writePage(RomBaseAddr,CurrentPos,CurrentPage) = FLASH_ERROR) then
begin
GotoXY(X,Y);
Writeln('Failed writing at page ',(CurrentPos div 128));
CurrentPos := Pred(BytesRead); {terminate loop}
Error := TRUE; {record error state}
end else begin
{programming that page succeeded - update screen and counters}
CurrentPos := CurrentPos + 128; {advance to the next page}
Percent := (CurrentPos*100) div BytesRead;
GotoXY(X,Y);
write(Percent,'%');
end;{if (writePage...}
end;{while}
end else begin
{byte-mode programming}
UpdateInt := BytesRead div 100;
for CurrentPos := 0 to Pred(BytesRead) do
begin
inc(UpdateCount);
if (UpdateCount = UpdateInt) then
begin
{update percentage displayed on-screen}
GotoXY(X,Y);
inc(Percent);
write(Percent,'%');
UpdateCount := 0;
end;{screen update}
if CurrentPos < 32768 then
CurrentByte := RomImage1^[CurrentPos]
else
CurrentByte := RomImage2^[CurrentPos-32768];
if (writeByte(RomBaseAddr,CurrentPos,CurrentByte) = FLASH_ERROR) then
begin
GotoXY(X,Y);
Writeln('Failed writing at byte ',CurrentPos);
CurrentPos := Pred(BytesRead); {terminate loop}
Error := TRUE; {record error state}
end;{if}
end;{for}
end;{if ChipType.../else}

if Not Error then begin
{write was OK; now check what's there}
GotoXY(X,Y);
WriteLn('OK ');
Write('Comparing... ');
Rom := Ptr( RomBaseAddr, 0 ); {access the ROM directly}
for CurrentPos := 0 to Pred(BytesRead) do
begin
if CurrentPos < 32768 then
CurrentByte := RomImage1^[CurrentPos]
else
CurrentByte := RomImage2^[CurrentPos-32768];
if Rom^[CurrentPos] <> CurrentByte then
begin
Error := True;
WriteLn('Error at offset ', WordToHex(CurrentPos), 'h');
CurrentPos := Pred(BytesRead);
end;{if}
end;{for}
If Not Error then WriteLn('OK!');
end;{if not error / else}
end;{if BytesRead > 0}
end {if eraseChip}
else
{chip erase failed}
WriteLn('Erase operation FAILED.');
Dispose(RomImage1); Dispose(RomImage2);
end;{procedure FlashChip}

function BaseOK( s : string ) : Boolean;
{checks that the base address i:
- in the correct range, A000 - F000
- 4K aligned
}
var
BaseAddr : Word;

begin
BaseAddr := HexToWord( s );
if ((BaseAddr AND $FF) = 0) and (BaseAddr >= $A000) and
(BaseAddr <= $F000) then
BaseOK := True
else
BaseOK := False;
end;{function BaseOK}

function ParamSpecified(s : string) : boolean;
{checks all command line arguments for s, returning true if found}
var i : word; found : boolean;
begin
found := false;
for i := 1 to ParamCount do
if Copy(ParamStr(i),1,Length(s)) = s then found := true;
ParamSpecified := found;
end;{function ParamSpecified}

Function ParamsOK( P1, P2 : string ) : Boolean;
{checks parameters, returns true if look OK}
var
f : file;
OK : Boolean;

begin
OK := True;
assign(f,P1);
{$i- } reset(f); {$i+ }
if IOResult <> 0 then begin
OK := False;
WriteLn('Couldn''t open file ', P1, '.');
end else begin
{found file OK}
close(f);
if not BaseOK(P2) then OK := False;
end;
if OK then
begin
{parameters suggest we're good to go - calibrate the timing loops}
write('Calibrating delay loops...');
calibrate_delay;
writeLn(' calibration factor is ', DelayCounter, '.');
end;{if OK}
ParamsOK := OK;
end;{function ParamsOK}

Procedure DisplayHelp;
begin
WriteLn('Supports SST 29xE010/39SF0x0, and AMIC A29010 flash chips.');
WriteLn;
WriteLn('Usage:');
WriteLn;
WriteLn('Write an image file to the ROM. The ROM is completely');
WriteLn('erased, then the file copied. Can be used with ROMs');
WriteLn('between 2KB and 64KB. Note: Checksum is not calculated.');
WriteLn;
WriteLn('eg: flash [image-file] [base-address]');
WriteLn;
WriteLn(' [image-file] - ROM image, i.e. xtide.bin');
WriteLn(' [base-address] - hex ROM window base address, i.e. D000');
WriteLn(' must be A000-F800');
WriteLn;
end;{procedure DisplayHelp}

var Ch : Char;

BEGIN
WriteLn('Lo-tech XT-CF and 8-bit ROM Board Flash Programmer, version ',VERSION);
If ParamsOK( ParamStr(1), ParamStr(2) ) then
begin
FlashChip( ParamStr(1), ParamStr(2) );
WriteLn;
WriteLn('If BIOS images currently in use have been updated, you MUST');
WriteLn('now reboot.');
WriteLn;
Write('Press any key to return to DOS, or CTRL-ALT-DEL to restart.');
{clear keyboard buffer, in case user interrupted the process}
while keypressed do Ch := ReadKey;
{now pause}
repeat until keypressed;
if keypressed then Ch := Readkey;
end
else DisplayHelp;
END.{program}
</source>

Lo-tech 1MB RAM Board

2023-01-14T10:07:54Z

James: /* DIP Switch Settings */ Amended to reflect bus contention issue with 5150 16-64KB system board.

[[File:Lo-tech-1MB-RAM-Board-assembled-r02.jpg|right|300px|Lo-tech 1MB RAM Board (r02), Assembled]]
The [[Lo-tech 1MB RAM Board]] is an 8-bit ISA expansion card providing up to 1MB of system RAM to [[IBM Personal Computer 5150|IBM compatible PCs]]. The small form factor makes the board suitable for the [[IBM Portable Computer 5155]].

This board can be purchased online via [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

Revision History:

*R01 - Prototype. See [[Lo-tech 1MB RAM Board (prototype) Resources]].
*R02 - First production release.

== Technical Description ==

The [[Lo-tech 1MB RAM Board]] utilises two [{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM chips] to provide 8Mb (=1MB) total RAM capacity, buffered via a 74HCT245 to ensure compatibility with TTL logic levels, on an 8-bit ISA expansion card.

DIP switches enable each 64KB physical page to be independently enabled, so making possible RAM expansion of all systems to the maximum 640KB, regardless of the size of the system board RAM fitted. To extend compatibility further, the first 16KB can be excluded, so providing compatibility with the [[IBM Personal Computer 5150]] when the system board is populated with the minimum 16KB RAM.

The board can also provide [http://en.wikipedia.org/wiki/Upper_memory_area upper memory] (between 640KB and 1MB) that, whilst not generally used by MS-DOS in an XT class machine, can be used for specific purposes such as TSRs, disk cache and print spoolers. Any complete unused physical pages can be populated by the RAM board for this purpose.

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:Lo-tech-1MB-RAM-Board-schematic-r02.png
File:1MB-RAM-Board-r02-Top.png
File:Lo-tech-1MB-RAM-Board-assembled-r02.jpg
</gallery>

*[{{SERVER}}/downloads/1MB-RAM-Board/AS6C4008.pdf AS6C4008-55SIN 4Mb static RAM datasheet]

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2014 Peacon Ltd.

=== Assembly ===

This PCB makes use of SMT components:

*SOIC chips have a pitch of 1.27mm
*0603 package capacitors and resistors

Assembly requires flux and a temperature controlled soldering station.

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|C1..C9 || 0.1uF || X7R Ceramic Capacitor || 0603 || 9 || 1414610 || C0603C104K4RACTU
|-
|C10 || 10uF || 16V Electrolytic || E2-5 || 1 || 9451056 || 140-REA100M1CBK0511P
|-
|IC1, IC2 || - || AS6C4008-55SIN 4Mb SRAM || SOIC-32 || 2 || 1562901 || 913-AS6C4008-55SIN
|-
|IC3, IC4 || - || 74HCT138D || SOIC-16 || 2 || 1201307 || 771-74HCT138D-T
|-
|IC5, IC6 || - || 74HCT30D || SOIC-20 || 2 || 1085303 || 771-HCT30D652
|-
|IC7 || - || 74HCT245DW || SOIC-20 || 1 || 1085315 || 771-74HCT245D
|-
|IC8 || - || 74LS05D || SOIC-14 || 1 || 9592164 || 595-SN74LS05D
|-
|IC9 || - || 74HCT02D || SOIC-14 || 1 || 1085298 || 595-SN74HCT02D
|-
|RN1..RN5 || 10k || RESISTOR, ARRAY-4, 10K, 1206 || 1206 || 5 || 1770137 || 652-CAY16-103J4LF
|-
|SW1, SW2 || - || MULTICOMP MCNDS-08-V || DIP-16 || 2 || 9471596 || 774-2068
|}

== ISA Bracket ==

Uses [[Lo-tech_ISA_Slot_Brackets#Type_3|Lo-tech ISA Slot Bracket Type 3]].

== DIP Switch Settings ==

The board is configured via two banks of DIP switches, which control whether each physical segment (=64KB) is active on the memory board.

Switch position ON enables the corresponding page:

{| class="wikitable"
!Sw1 !!Sw2
|-
|
{| class="wikitable"
!Position !!Page !! Memory Range
|-
| 1.1 || 0000h || 0-64KB (16-64KB when Sw2.8 ON)
|-
| 1.2 || 1000h || 64-128KB
|-
| 1.3 || 2000h || 128-192KB
|-
| 1.4 || 3000h || 192-256KB
|-
| 1.5 || 4000h || 256-320KB
|-
| 1.6 || 5000h || 320-384KB
|-
| 1.7 || 6000h || 384-448KB
|-
| 1.8 || 7000h || 448-512KB
|}
|
{| class="wikitable"
!Position !!Page !! Memory Range
|-
| 2.1 || 8000h || 512-576KB
|-
| 2.2 || 9000h || 576-640KB
|-
| 2.3 || A000h || 640-704KB
|-
| 2.4 || B000h || 704-768KB
|-
| 2.5 || C000h || 768-832KB
|-
| 2.6 || D000h || 832-896KB
|-
| 2.7 || E000h || 896-960KB
|-
| 2.8 || - || Disables 0-16KB (when Sw1.1 ON)
|}
|-
|}
Note that when used with IBM 5150 16-64KB system board, the system board should be populated with 64KB to avoid bus contention.

== See Also ==

*[[Lo-tech Memory Boards]]
*[[Lo-tech Memory Board FAQ]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech ISA CompactFlash Adapter revision 2b

2022-08-19T07:04:33Z

James: /* BIOS Flashing (Programming) */

The [[Lo-tech ISA CompactFlash Adapter revision 2b]] is a bootable storage adapter for IBM PC, PC/XT, PC/AT and compatible hardware - essentially any PC with an ISA slot. The card enables the use of:

*Standard CompactFlash cards, via any low-cost CompactFlash to IDE adapter
*SD-Cards, via an FC1306T based SD to IDE adapter
*ATA-2 compliant hard disks

<gallery widths="200px" heights="150px" perrow="4">
File:ISA-CompactFlash-Adapter-PCB-Front-r2b.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-front-assembled.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-back.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-back-assembled.JPG
</gallery>

For help getting this kit running, please see the [[Lo-tech ISA CompactFlash Adapter FAQ]] or [{{SERVER}}/get-in-touch/ Get In touch].

The BIOS ROM on the card enables the host PC to boot from storage presented by the adapter, which appears in DOS as an ordinary fixed disk (i.e. drive C, D, etc). No DOS drivers are needed.

The PCB itself is a through-hole, small form factor 8-bit ISA adapter. No slot bracket is needed, due to the small size. The design provides:

*Bootable storage adapter for 8-bit PCs
*Ease of home assembly, by use of only through-hole components for basic operation
*Small form-factor, to enable use in machines with limited expansion slot space such as the Tandy 1000HX, Sinclair PC200 and Amstrad PC-20
*[[IBM Personal Computer XT System Board Slot 8]] compatibility (with optional SMD components mounted on rear of PCB)
*5V supply to IDE header key-pin, for cable-less operation of CompactFlash and SD-Card adapters supporting this power option
*Selectable BIOS address - C800h or D800h

The board is programatically identical to the [[XT-CF-lite]] and uses the [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS], provided through an in-system re-programmable 32KB flash-based ROM. Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable - the board can therefore function as a universal ROM board.

''Please note that ATA and SATA hard drives cannot be used with this adapter, except ATA-2 compliant drives. The [[Lo-tech 8-bit IDE Adapter]] is compatible with standard ATA and SATA drives.''

To buy this and other PCBs, please visit [{{SERVER}}/shop the lo-tech shop].

== Specifications ==

=== General ===

*8-bit ISA card with 40-pin IDE header for attachment to:
**IDE to CompactFlash adapter
**FC1306T based IDE to SD Card adapter
**ATA-2 compliant drives
*5V power supply:
**to IDE header key-pin (can drive micro-drives, CompactFlash adapters and SD Card adapters without any external power connection)
**holes for attachment of peripheral power cable (for use where target host has no available peripheral power cables)
*Basic functionality is dependent only on through-hole components
*Optional SMT components provide additional functionality:
**Line driver for external activity LEDs (12mA power budget for external LED)
**[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Utilises [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS] (adapter type: 'XT-CF')
*Resource requirements:
**IO ports 300-31Fh
**ROM: 32KB at C800h or D800h

== Design ==

<gallery widths="200px" heights="150px" perrow="4">
File:Lo-tech-ISA-CompactFlash-Adapter-rev2b-Schematic.png
File:ISA-CompactFlash-Adapter-PCB-Front-r2b.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-back.JPG
File:lo-tech-isa-compactflash-adapter-revision-2b-front-assembled.JPG
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2013,2016 Peacon Ltd.

== Bill of Materials ==

=== Core Components ===

Basic functionality requires only through-hole components. JP2 must be closed, and ROM address will be fixed at C800h.

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC3 || 74HCT688N || DIP-20 || 2 || 382504 || 771-74HCT688N
|-
|IC2 || SST39SF010A-70-4C-PHE || DIP-32 || 1 || 1896595 || 804-39SF010A7CPHE
|-
|IC4 || 74HCT139N || DIP-16 || 1 || 382036 || 595-SN74HCT139N
|-
|IC5 || 74HCT245N || DIP-20 || 1 || 9591931 || 595-SN74HCT245N
|-
|RN1 || 4-element Isolated Resistor Network, 10k || SIP-8 || 1 || 9356525 || 652-4608X-2LF-10K
|-
|C1..5 || 0.1uF Ceramic Capacitor || C025-030X050 || 5 || 2112751 || 581-SR205E104MAR or 581-SR205C104KAR
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || 647-UVR1C100MDD
|-
|C8 || 2.2uF Tanalum Capacitor || - || 1 || DNP* || DNP*
|-
|HD1 || T821140A1S100CEU || 2x20 Pin Header, 2.54mm spacing || 1 || 2215314 || 517-30340-6002
|-
|IC Socket (DIP32) || - || DIL32 || 1 || 1654375 || 571-1-2199300-2 517-4832-6000-CP
|-
|IC Socket (DIP20) || - || DIL20 || 3 || 1101349 || 571-1-2199298-6 649-DILB20P-223TLF
|-
|IC Socket (DIP16) || - || DIL16 || 1 || 1101347 || 571-1-2199298-4 649-DILB16P-223TLF
|-
|JP1, JP2, JP3 || - || 1x2 Pin Header || 3 || 1593411 || 855-M20-9990246 653-XG8S-0231
|-
| - || - || 2-pin jumper || 2 || 2396301 || 806-SX1100-A
|}

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
**AMIC chips appear to have been discontinued (as as Nov-13)
*Regardless of the chip used, 32KB is presented at C800h (JP2 closed) or D800h (JP2 open and R4 fitted)
*DNP = Do Not Populate

=== Enhanced Functionality ===

Additional components are required for:

*[[IBM Personal Computer XT System Board Slot 8]] compatibility (also provides enhanced read performance for PC/AT systems)
*Device activity LED
*ROM address selection (C800h/D800h)

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|U1 || SN74LS33D || SOIC-14 || 1 || 1752958 || 595-SN74LS33D
|-
|R1, R2, R4 || RESISTOR, 10K, 125MW || 0805 || 3 || 1612522 || 71-CRCW0805J-10K-E3
|-
|R3 || RESISTOR, 0.125W 1% 270R || 0805 || 1 || 1652970 || 71-CRCW0805270RJNEA
|-
|C7 || CAPACITOR, 0.1UF, 50V || 0805 || 1 || 1612208 || VJ0805V104MXBPW1BC
|-
|LED || - || 1x2 Pin Header || 1 || 1593411 || 855-M20-9990246
|}

Note that when assembling SMT components, additional flux will also be needed (such as Edsyn FL22, Farnell order code 3059091).

== Configuration ==

*JP1: ROM enable (closed = enabled)
*JP2: ROM Address Selection - closed = C800h, open (and R4 fitted) = D800h
*JP3: Slot-8/ZWS Function (closed = enabled) - requires SMT components

An external LED can be attached to the 2-pin LED header only if the optional components (on the rear of the PCB) are populated. Current limit for LED is 12mA.

The IO port address (300h - 31Fh) is fixed.

== Build & Test ==

For additional help, please email me via [{{SERVER}}/get-in-touch/ the site blog].

=== General ===

This project is available in [{{SERVER}}/shop the Lo-tech store] as [{{SERVER}}/product/lo-tech-isa-compactflash-pcb/ a Bare PCB] - components from the Bill of Materials above must be sourced separately for example from Farnell, Newark, Mouser, DigiKey or other electronic component supplier. Farnell and Newark part numbers are provided above for convenience.

An appropriate media adapter and storage device must be purchased separately (i.e. and IDE to CompactFlash adapter and a CompactFlash card).

A temperature controlled soldering iron is highly recommended for assembly. Tin-lead solder is generally easier to use than lead-free. A quality syringe flux is also recommended and is essential for the optional SMT parts (see [[SMT Soldering Notes]]). Before construction, the PCB should be cleaned in isopropynol.

=== Construction ===

*Find a suitable work surface with plenty of light. I find a car-cleaning sponge useful to rest the PCB on since components are held nicely in place under the PCB by the soft surface, which can also be easily turned around as a whole with components not yet soldered
*Start with the least tall components, so that they are held full in place with the solder side up
*When soldering IC sockets or ICs, ensure the notches are at the correct end as indicated by the PCB silkscreen
*If using a shrouded 40-pin header, observe correct orientation as indicated by the silkscreen. The key pin can be removed from the header with a small pair of thin-nose pliers before placement (though note that the key pin can be used to supply 5V to the required CompactFlash adapter if left in-place)
*Note the correct orientation of the polarised capacitors C6 and C8. C8 positive leg is closest to C3.
*Wash all flux residues off once complete using isopropynol (for example with a toothbrush)
*Check closely with a magnifying glass all joints. Check especially for bridges between SMT pins

=== BIOS Flashing (Programming) ===

''The following assumes JP2 is closed, providing the ROM at C800h''

*The board is powered by the [[XTIDE Universal BIOS]] and features a 32KB in-system re-programmable flash chip
*XTIDE Universal BIOS build R560 or newer is recommended (v2 beta 3 is much older)
**[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip Pre-configured BIOS based on R566 - BIOS at C800h]
**[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/offr566.zip Pre-configured BIOS based on R566 - FFh padded with BIOS at CC00h] - see [[Lo-tech_ISA_CompactFlash_Adapter_FAQ#What_BIOS_does_the_Card_Use.3F|FAQ]] for more information
*The flash chip is programmed with the [[Lo-tech XT-CF flash utility]]
*Select the appropriate ROM image:
**IDE_XT.BIN for Intel 8088 and 8086 CPUs
**IDE_XTP.BIN for NEC V20, V30, and Intel 80286 CPUs

'''Note: The late initialisation module in the XTIDE Universal BIOS should only be included in the BIOS build for systems that require this. The module can cause the BIOS to hang after initialisation on other systems. The BIOS build above excludes this module.'''

To program the board, make a DOS boot disk (utilities have been tested on MS-DOS 2.11, 3.3 and 6.22) and add the BIOS binary file and the flash utility. Install the Lo-tech ISA CompactFlash Adapter in the machine and boot from the floppy, then flash the ROM thus:

A:\>flash ide_xt.bin c800

Note that should a board containing the IDE_XTP.BIN image be moved to an Intel 8088/8086 PC, the BIOS image will cause the machine to hang during the POST. To resolve this, either re-flash the board with the IDE_XT.BIN image before moving, or disable the ROM during the POST via JP1. JP1 can be closed once the machine has booted, so enabling the ROM for programming (provided there is no other ROM at C800h).

=== Configuration ===

In addition to the board configurable options, the XTIDE Universal BIOS provides several transfer modes for [[Lo-tech XT-CF Boards]]. The [[Lo-tech ISA CompactFlash Adapter revision 2]] supports two modes (PIO and BIU), which can be changed on-the-fly with the [[Lo-tech XTCFMODE Utility]]. The default mode, set when the BIOS is initialised (i.e. when the machine is powered-on or rebooted), is set within the BIOS via the XTIDE Universal BIOS <tt>xtidecfg.com</tt> utility.

Since the transfer mode reverts at every reboot to the mode set in the BIOS, to permanently set the transfer mode it should be configured accordingly within the BIOS. Alternatively, [[XTCFMODE]] can be included in <tt>AUTOEXEC.BAT</tt>.

For PC/AT class hardware, the use of BIU mode and enabling slot-8/ZWS function (requires optional SMT components and JP3 closed), read performance of up to 1MB/s can be achieved.

== See Also ==

*[[Lo-tech ISA CompactFlash Adapter FAQ]]
*[[lo-tech XT-CF Boards]]

Lo-tech ISA USB Adapter

2022-08-18T12:35:18Z

James: /* Downloads */

[[File:Lo-tech-ISA-USB-Adapter-PCB-Front.JPG|right|300px|Lo-tech ISA USB Adapter PCB]]

The [[Lo-tech ISA USB Adapter]] is a bootable storage adapter for IBM PC, PC/XT, PC/AT and compatible hardware - essentially any PC with an ISA slot, enabling a standard USB flash drive to be used. This eliminates the dependence on ageing hard disks and floppy disks, and makes data exchange with a modern PC easy. The design is based on the CH375 USB chip and is a development of the [[Lo-tech ISA CompactFlash Adapter revision 2b]].

The BIOS ROM used by the card (available [https://gitlab.com/hakfoo1/v40-bios/-/tree/CH375-Workarounds/ here]) enable the host PC to boot from storage presented by the adapter, which appears in DOS as an ordinary fixed disk (i.e., drive C, D, etc). No DOS drivers are needed. Note that the maximum partition size under MS-DOS is 2GB, meaning a total of 8GB can be accessed and the current BIOS provides up to 504MB. For users not requiring ROM boot, a CONFIG.SYS driver will also be available soon.

The PCB itself is a 4-layer, small form factor 8-bit ISA adapter. Building this PCB requires some surface-mount (SMT) components, the smallest being 0603 capacitors. Mounting holes are provided for a custom ISA slot bracket, which can be 3D printed in plastic at home, or from commercial vendors in various metals.

The design provides:

*Bootable storage adapter for 8-bit PCs
*Small form-factor, to enable use in machines with limited expansion slot space such as the Tandy 1000HX, Sinclair PC200 and Amstrad PC-20
*[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Selectable BIOS address - C800h or D800h

The BIOS is provided through an in-system re-programmable 32KB flash-based ROM, and since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable - the board can therefore function as a universal ROM board.

The board uses the CH375 USB interface and provides optimised transfer speed for PC/XT class machines by using shifted port mapping, so enabling 16-bit instructions. This improves the performance to about 170KB/s at 4.77MHz.

== Specifications ==

=== General ===

*8-bit ISA card with standard USB socket for connection of USB flash drive
*Line driver for external activity LEDs (12mA power budget)
*[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Resource requirements:
**IO ports 2C0-2C8h
**ROM: 32KB at C800h or D800h

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:Lo-tech-ISA-USB-adapter-schematic.png
File:Lo-tech-ISA-USB-Adapter-PCB-Front.JPG
File:Lo-tech-ISA-USB-Adapter-PCB-Back.JPG
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''.

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC3 || 74HCT688N || DIP-20 || 2 || 382504 || 771-74HCT688N
|-
|IC2 || SST39SF010A-70-4C-PHE || DIP-32 || 1 || 1896595 || 804-39SF010A7CPHE
|-
|IC4 || CH375 || SOIC-28 || 1 || - || -
|-
|IC5 || 74HCT245N || DIP-20 || 1 || 9591931 || 595-SN74HCT245N
|-
|C1-3, C5 || 0.1uF Ceramic Capacitor || C025-030X050 || 4 || 2112751 || 581-SR205E104MAR or 581-SR205C104KAR
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || 647-UVR1C100MDD
|-
|C7 || CAPACITOR, 0.1UF, 50V || 0805 || 2 || 1612208 || VJ0805V104MXBPW1BC
|-
|C9 || 0.01uF Ceramic || 0603 || 1 || - || 963-UMK107B7103KAHT
|-
|C10 || 0.1uF Ceramic || 0603 || 2 || - || 963-UMK107BJ104KAHT
|-
|C12-13 || 15-30pF Ceramic || 0603 || 2 || || 581-06035C220JAT2A
|-
|C14, C15 || 100uF Electrolytic Capacitor || E2-5 || 1 || - || 647-UVR1A101MDD
|-
|IC Socket (DIP32) || - || DIL32 || 1 || 1654375 || 571-1-2199300-2 517-4832-6000-CP
|-
|IC Socket (DIP20) || - || DIL20 || 3 || 1101349 || 571-1-2199298-6 649-DILB20P-223TLF
|-
|JP1, JP2, JP3, LED || - || 1x2 Pin Header || 4 || 1593411 || 855-M20-9990246 653-XG8S-0231
|-
|JP4 || - || 2x2 Pin Header || 1 || - || 517-9612046804AR
|-
| - || - || 2-pin jumper || 4 || 2396301 || 806-SX1100-A
|-
|U1 || SN74LS33D || SOIC-14 || 1 || 1752958 || 595-SN74LS33D
|-
|R1, R2, R4 || RESISTOR, 10K, 125MW || 0805 || 3 || 1612522 || 71-CRCW0805J-10K-E3
|-
|R3 || RESISTOR, 0.125W 1% 270R || 0805 || 1 || 1652970 || 71-CRCW0805270RJNEA
|-
|R5 || RESISTOR, 0.125W 1% 2R || 0805 || 1 || 1652970 || 71-CRCW08052R00FKEA
|-
|R6 || RESISTOR, 10K, 125MW || 0204/7 || 1 || 9342419 || 270-10K-RC
|-
|X1 || HC49 Crystal, 12MHz ±0.4‰ || - || 1 || - || 774-ATS12A-E
|-
|HD1 || USB Connectors RA USB A || - || 1 || - || 523-UE27AC5410H
|}

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
**AMIC chips appear to have been discontinued (as as Nov-13)
*Regardless of the chip used, 32KB is presented at C800h (JP2 closed) or D800h (JP2 open and R4 fitted)

Note that when assembling SMT components, additional flux will also be needed (such as Edsyn FL22, Farnell order code 3059091).

== Configuration ==

*JP1: ROM enable (closed = enabled)
*JP2: ROM Address Selection - closed = C800h, open (and R4 fitted) = D800h
*JP3: Slot-8/ZWS Function (closed = enabled) - requires SMT components
*JP4: Port mode
**Std - 8-bit transfers, registers mapped at 2C0h, 2C1h
**Fast - 16-bit transfers, registers mapped at 2C0h, 2C2h (not supported by alpha BIOS)

An external LED can be attached to the 2-pin LED header only if the optional components (on the rear of the PCB) are populated. Current limit for LED is 12mA.

The IO port address (2C0h - 2C8h) is fixed.

== Build & Test ==

For additional help, please [{{SERVER}}/get-in-touch/ send an email].

=== Construction ===

*Find a suitable work surface with plenty of light. A car-cleaning sponge is useful to rest the PCB on since components are held nicely in place under the PCB by the soft surface, which can also be easily turned around as a whole with components not yet soldered
*Start with the SMT components, then proceed with the least tall components, so that they are held full in place with the solder side up
*When soldering IC sockets or ICs, ensure the notches are at the correct end as indicated by the PCB silkscreen
*Note the correct orientation of the polarised capacitors C6, C14 and C15.
*Wash all flux residues off once complete using isopropynol (for example with a toothbrush)
*Check closely with a magnifying glass all joints. Check especially for bridges between SMT pins

=== BIOS Flashing (Programming) ===

''The following assumes JP2 is closed, providing the ROM at C800h''

The flash chip is programmed with the [[Lo-tech XT-CF flash utility]]. To program the board, make a DOS boot disk (utilities have been tested on MS-DOS 2.11, 3.3 and 6.22) and add the BIOS binary file and the flash utility. Install the Lo-tech ISA CompactFlash Adapter in the machine and boot from the floppy, then flash the ROM thus:

A:\>flash v40-bios.bin c800

== Errata ==

The silkscreen incorrectly documents the fixed IO port range as 260-26Fh; the CH375 is at 2C0h.

== Downloads ==

*[https://gitlab.com/hakfoo1/v40-bios Boot ROM by Hakfoo]
*[{{SERVER}}/downloads/isa-usb/CH375-datasheet.pdf CH375 datasheet]

Config.sys driver (for non-bootable use) coming soon.

== See Also ==

*[[Lo-tech ISA USB Adapter FAQ]]
*[[lo-tech XT-CF Boards]]

Lo-tech ISA Slot Brackets

2022-08-18T06:45:50Z

James: Added STL file download links

Custom designed ISA slot brackets for Lo-tech PCBs:

== Type 1 ==
<gallery widths="200px" heights="150px" perrow="3">
File:peacon-xt-cf-bracket.png
File:xt-cf-isa-slot-bracket-1.jpg
File:xt-cf-isa-slot-bracket-2.jpg
</gallery>

*Used by: [[XT-CF]], [[XT-CFv2]], [[XT-CFv3]], [[XT-CF-lite]]
*[{{SERVER}}/downloads/ISA-Slot-Brackets/XT-CF-Bracket-Type-1-r01.stl Type 1 Bracket STL Design File]

== Type 2 ==

<gallery widths="200px" heights="150px" perrow="3">
File:lo-tech-isa-slot-bracket-type-2-design.png
File:Lo-tech-ISA-Slot-Bracket-Type-2.jpg
</gallery>
*Used by: [[XT-CF-lite rev.2]]
*[{{SERVER}}/downloads/ISA-Slot-Brackets/XT-CF-Bracket-Type-2-r04.stl Type 2 Bracket STL Design File]

== Type 3 ==

<gallery widths="200px" heights="150px" perrow="3">
File:RAM-and-EMS-Board-Slot-Bracket-r01.png
File:Lo-tech-ISA-Slot-Bracket-Type-3-Design.png
File:Lo-tech-ISA-Slot-Bracket-Type-3.jpg
</gallery>

*Used by: [[Lo-tech 8-bit IDE Adapter|8-bit IDE Adapter]], [[Lo-tech 1MB RAM Board|1MB RAM Board]], [[Lo-tech 2MB EMS Board|2MB EMS Board]]
*[{{SERVER}}/downloads/ISA-Slot-Brackets/XT-CF-Bracket-Type-3-r02.stl Type 3 Bracket STL Design File]

== See Also ==

*[[Main Page]]

CompactFlash Adapter for Tandy 1400 Laptops

2022-08-17T18:06:00Z

James:

[[File:CompactFlash-Adapter-for-Tandy-1400-Laptops-assembled.JPG|right|300px|CompactFlash Adapter for Tandy 1400 Laptops]]

The [[CompactFlash Adapter for Tandy 1400 Laptops]] is a system specific [[Lo-tech XT-CF Boards|XT-CF]] variant for [[Tandy 1400 Series Laptops]]:

*[[Tandy 1400LT]] models using BIOS version 2.51, and
*[[Tandy 1400FD|Tandy 1400FD/HD]] models using BIOS version 1.04

The board is programatically identical to the [[XT-CF-lite]] and is therefore powered by the [[XTIDE Universal BIOS]], provided through an in-system re-programmable 32KB (addressible) flash-based ROM. Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable.

Note: It is not currently known whether the 2.51 BIOS version can be used in earlier 1400LT models. The BIOS image is however [{{SERVER}}/downloads/BIOS/Tandy/LT1400_BIOS_2.51.70.zip available for download here].

To buy this and other PCBs, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

== Specifications ==

=== General ===

*8-bit [[Tandy_1400_Series_Expansion_Slots#Expansion_Slot|Tandy 1400 Series Expansion Slot Card]] with CompactFlash header
*Entirely 5V CMOS logic
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Utilises [[XTIDE Universal BIOS]] (XTplus build; adapter type: 'XT-CF')
*Fixed resource allocation - IO ports 300-31Fh, ROM 32KB at C800h
*Compatible with any CompactFlash card (microdrives are not supported due to power budget limitation from the Tandy 1400 expansion slot)

== PCB ==

[[File:CompactFlash-Adapter-for-Tandy-1400-Laptops-pcb.jpg|right|300px|CompactFlash Adapter for Tandy 1400 Laptops PCB]]

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC2 || 74HCT688D || SOIC-20W || 2 || 1085321 || -
|-
|IC3 || 74HCT139D || SOIC-16 || 1 || 9591834 || -
|-
|IC4 || AMIC - A29010-70F || DIP-32 || 1 || 1907092 || -
|-
|R1, R2, R4 || 10k Resistor || 0603 || 3 || 1469748 || -
|-
|R3 || Do not populate || - || - || - || -
|-
|R5* || 1k6 Resistor || 0603 || 1 || 2138367 || -
|-
|C1..5 || 0.1uF Ceramic Capacitor || 0603 || 5 || 1414610 || -
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || -
|-
|CF1 || 3M NE750-Q516RB-50 CompactFlash Header || - || 1 || 1267444 || -
|-
|IC Socket || - || DIL32 || 1 || 1654375 || 571-1-390263-2
|-
|JP1, LED* || AMP - 826629-2 || 1x2 Pin Header || 2 || 3418285 || -
|}

<nowiki>*</nowiki>Components only needed if activity LED is required

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
*Regardless of the chip used, 32KB is presented commencing C800h

== Configuration ==

*JP1: ROM enable (closed = enabled)
*An external LED can be attached to the 2-pin LED header, but a low-current type must be used (approx. 2mA available).
*The IO port address (300h - 31Fh) is fixed, as is the ROM address (32KB at C800h) - note therefore the board cannot co-exist with the [[Tandy 1400HD]] MFM disk controller
*Pre-configured BIOS based on XTIDE Universal BIOS r567 is available [{{SERVER}}/downloads/XT-CF/ISA-CF-BIOS-r567-late-init.zip here]
*The flash ROM can be programmed with the [[Lo-tech XT-CF flash utility]]

== See Also ==

*[[lo-tech XT-CF Boards]]
*[[Tandy 1400 Series Laptops]]

CompactFlash Adapter for Tandy 1400 Laptops

2022-08-17T17:57:05Z

James:

[[File:CompactFlash-Adapter-for-Tandy-1400-Laptops-assembled.JPG|right|300px|CompactFlash Adapter for Tandy 1400 Laptops]]

The [[CompactFlash Adapter for Tandy 1400 Laptops]] is a system specific [[Lo-tech XT-CF Boards|XT-CF]] variant for [[Tandy 1400 Series Laptops]]:

*[[Tandy 1400LT]] models using BIOS version 2.51, and
*[[Tandy 1400FD|Tandy 1400FD/HD]] models using BIOS version 1.04

The board is programatically identical to the [[XT-CF-lite]] and is therefore powered by the [[XTIDE Universal BIOS]], provided through an in-system re-programmable 32KB (addressible) flash-based ROM. Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable.

Note: It is not currently known whether the 2.51 BIOS version can be used in earlier 1400LT models. The BIOS image is however [{{SERVER}}/downloads/BIOS/Tandy/LT1400_BIOS_2.51.70.zip available for download here].

To buy this and other PCBs, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

== Specifications ==

=== General ===

*8-bit [[Tandy_1400_Series_Expansion_Slots#Expansion_Slot|Tandy 1400 Series Expansion Slot Card]] with CompactFlash header
*Entirely 5V CMOS logic
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Utilises [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS] (XTplus build; adapter type: 'XT-CF')
*Fixed resource allocation - IO ports 300-31Fh, ROM 32KB at C800h
*Compatible with any CompactFlash card (microdrives are not supported due to power budget limitation from the Tandy 1400 expansion slot)

== PCB ==

[[File:CompactFlash-Adapter-for-Tandy-1400-Laptops-pcb.jpg|right|300px|CompactFlash Adapter for Tandy 1400 Laptops PCB]]

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC2 || 74HCT688D || SOIC-20W || 2 || 1085321 || -
|-
|IC3 || 74HCT139D || SOIC-16 || 1 || 9591834 || -
|-
|IC4 || AMIC - A29010-70F || DIP-32 || 1 || 1907092 || -
|-
|R1, R2, R4 || 10k Resistor || 0603 || 3 || 1469748 || -
|-
|R3 || Do not populate || - || - || - || -
|-
|R5* || 1k6 Resistor || 0603 || 1 || 2138367 || -
|-
|C1..5 || 0.1uF Ceramic Capacitor || 0603 || 5 || 1414610 || -
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || -
|-
|CF1 || 3M NE750-Q516RB-50 CompactFlash Header || - || 1 || 1267444 || -
|-
|IC Socket || - || DIL32 || 1 || 1654375 || 571-1-390263-2
|-
|JP1, LED* || AMP - 826629-2 || 1x2 Pin Header || 2 || 3418285 || -
|}

<nowiki>*</nowiki>Components only needed if activity LED is required

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
*Regardless of the chip used, 32KB is presented commencing C800h

== Configuration ==

*JP1: ROM enable (closed = enabled)
*An external LED can be attached to the 2-pin LED header, but a low-current type must be used (approx. 2mA available).
*The IO port address (300h - 31Fh) is fixed, as is the ROM address (32KB at C800h) - note therefore the board cannot co-exist with the [[Tandy 1400HD]] MFM disk controller
*Pre-configured BIOS based on XTIDE Universal BIOS r567 is available [{{SERVER}}/downloads/XT-CF/ISA-CF-BIOS-r567-late-init.zip here]
*The flash ROM can be programmed with the [[Lo-tech XT-CF flash utility]]

== See Also ==

*[[lo-tech XT-CF Boards]]
*[[Tandy 1400 Series Laptops]]

CompactFlash Adapter for Tandy 1400 Laptops

2022-08-17T17:55:55Z

James: Added LT compatibility node

[[File:CompactFlash-Adapter-for-Tandy-1400-Laptops-assembled.JPG|right|300px|CompactFlash Adapter for Tandy 1400 Laptops]]

The [[CompactFlash Adapter for Tandy 1400 Laptops]] is a system specific [[Lo-tech XT-CF Boards|XT-CF]] variant for [[Tandy 1400 Series Laptops]]:

*1400LT models using BIOS version 2.51, and
*1400FD/HD models using BIOS version 1.04

The board is programatically identical to the [[XT-CF-lite]] and is therefore powered by the [[XTIDE Universal BIOS]], provided through an in-system re-programmable 32KB (addressible) flash-based ROM. Since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable.

Note: It is not currently known whether the 2.51 BIOS version can be used in earlier 1400LT models. The BIOS image is however [{{SERVER}}/downloads/BIOS/Tandy/LT1400_BIOS_2.51.70.zip available for download here].

To buy this and other PCBs, please visit [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

== Specifications ==

=== General ===

*8-bit [[Tandy_1400_Series_Expansion_Slots#Expansion_Slot|Tandy 1400 Series Expansion Slot Card]] with CompactFlash header
*Entirely 5V CMOS logic
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Utilises [http://code.google.com/p/xtideuniversalbios/ XT-IDE Universal BIOS] (XTplus build; adapter type: 'XT-CF')
*Fixed resource allocation - IO ports 300-31Fh, ROM 32KB at C800h
*Compatible with any CompactFlash card (microdrives are not supported due to power budget limitation from the Tandy 1400 expansion slot)

== PCB ==

[[File:CompactFlash-Adapter-for-Tandy-1400-Laptops-pcb.jpg|right|300px|CompactFlash Adapter for Tandy 1400 Laptops PCB]]

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC2 || 74HCT688D || SOIC-20W || 2 || 1085321 || -
|-
|IC3 || 74HCT139D || SOIC-16 || 1 || 9591834 || -
|-
|IC4 || AMIC - A29010-70F || DIP-32 || 1 || 1907092 || -
|-
|R1, R2, R4 || 10k Resistor || 0603 || 3 || 1469748 || -
|-
|R3 || Do not populate || - || - || - || -
|-
|R5* || 1k6 Resistor || 0603 || 1 || 2138367 || -
|-
|C1..5 || 0.1uF Ceramic Capacitor || 0603 || 5 || 1414610 || -
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || -
|-
|CF1 || 3M NE750-Q516RB-50 CompactFlash Header || - || 1 || 1267444 || -
|-
|IC Socket || - || DIL32 || 1 || 1654375 || 571-1-390263-2
|-
|JP1, LED* || AMP - 826629-2 || 1x2 Pin Header || 2 || 3418285 || -
|}

<nowiki>*</nowiki>Components only needed if activity LED is required

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
*Regardless of the chip used, 32KB is presented commencing C800h

== Configuration ==

*JP1: ROM enable (closed = enabled)
*An external LED can be attached to the 2-pin LED header, but a low-current type must be used (approx. 2mA available).
*The IO port address (300h - 31Fh) is fixed, as is the ROM address (32KB at C800h) - note therefore the board cannot co-exist with the [[Tandy 1400HD]] MFM disk controller
*Pre-configured BIOS based on XTIDE Universal BIOS r567 is available [{{SERVER}}/downloads/XT-CF/ISA-CF-BIOS-r567-late-init.zip here]
*The flash ROM can be programmed with the [[Lo-tech XT-CF flash utility]]

== See Also ==

*[[lo-tech XT-CF Boards]]
*[[Tandy 1400 Series Laptops]]

Tandy 1400LT

2022-08-17T17:51:57Z

James: Added link to LT BIOS that supports the Lo-tech XT-CF for 1400s

[[file:tandy-1400lt.jpg|200px|right|thumb|Tandy 1400LT]]
The Tandy 1400LT was a [[Tandy 1400 Series Laptops|Tandy 1400 Series]] computer with an [[NEC V20]] CPU, two 720K floppy drives, and 768KB RAM.

The system was superceded by the similar [[Tandy 1400FD|1400FD]].

[[file:Tandy-1400LT-Catalogue-Page-1988.jpg|200px|right|thumb|Tandy 1400LT Catalogue Page]]

== Reference Material ==

*[{{SERVER}}/downloads/manuals/tandy/Tandy_1400LT_Quick_Reference_Guide.pdf Tandy 1400LT Quick Reference Guide]
*[[Tandy 1400 Series Expansion Slots]]
*[{{SERVER}}/downloads/manuals/tandy/Tandy_1400LT_Service_Manual.pdf Tandy 1400LT Service Manual] (large file; please be patient)
*[{{SERVER}}/downloads/BIOS/Tandy/LT1400_BIOS_2.51.70.zip Tandy 1400LT BIOS version 2.51.70] - the [[CompactFlash Adapter for Tandy 1400 Laptops]] can be used in 1400LT machines with this BIOS

== See Also ==

*[[Tandy 1400 Series Laptops]]
*[[CompactFlash Adapter for Tandy 1400 Laptops]]

Lo-tech XT-CF Board

2022-08-17T17:41:16Z

James: /* See Also */

[[File:Peacon-xt-cf-assembled.JPG|right|300px|Lo-tech XT-CF Board Assembled (first prototype)]]
The [[lo-tech XT-CF Board]] is a bootable 8-bit ISA card with a CompactFlash header mounted so that the CF card is accessible through a [[#ISA Bracket|custom ISA expansion slot bracket]]. This card has been designed for use in IBM PC/XT, PC/AT and all compatible systems.

''Note: the current iteration of this card is the [[XT-CFv3]].''

Key Features:

*Replace dead MFM or RLL hard disks (and their controllers) with a cheap CompactFlash or microdrive media
*Easy to access CompactFlash card without opening the PC
*Reduce system power consumption (and hence load on the PSU) by as much as 30W
*Uses the [https://xtideuniversalbios.org/ XT-IDE Universal BIOS] (adapter type 'lo-tech XT-CF')
*Increase system performance - offers 5x the throughput of an [[ST-412]]
*32K in-system re-programmable ROM (24K free for any other ROM code)

The board is derived from the [[Dangerous Prototypes XT-IDE Boards | Dangerous Prototypes V2 board]], and uses the same Xilinx XC9572XL CPLD.

== Specifications ==

=== General ===

*8-bit ISA card with header for type-I or type-II CompactFlash media
*CompactFlash header configured to operate media in true-IDE mode
*500mA 3.3V regulator can drive microdrive or CompactFlash cards without any external power connection (330mA power budget for microdrives)
*Line driver for on-card and external activity LEDs (30mA power budget for external LED)
*Low-cost SMT Flash memory chip with 32K usable
*JTAG header for CPLD programming

=== Modes of Operation ===

*8-bit Port-mapped IO
*16-but Port-mapped IO (supported on most systems; provides a performance advantage with 8088 and 8086 CPUs)

Operating mode is configured in the BIOS and can be switched on-the-fly between modes using the [[lo-tech XT-CF Configuration Utility]]. The board is functionality identical to the [[XT-CF-lite]], and with one jumper-wire fitted can also implement ISA B8 line functionality of the XT-CFv2, allowing use in [[IBM Personal Computer XT System Board Slot 8]].

== PCB ==

[[File:Peacon-xt-cf.JPG|right|300px|Lo-tech XT-CF Board]]

=== Boardhouse Requirements ===

*8 mils clearances and minimum track width
*0.4mm minimum hole size
*Can be manufactured on a 100x100mm board
*Gold fingers are preferable but not required

=== Assembly Notes ===

*Thoroughly wash the PCB before assembly with Isopropynol
*Place the CF socket, CPLD and flash chip first
*Next place the VRM, LED driver and resistor networks
*Then place LEDs, resistors and SMT capacitors
*Next thoroughly wash the board using a toothbrush to ensure flux is removed from between SMT pins
*Next add the through-hole components (DIP switch, headers and 47uF capacitor), then wash again
*Before use inspect all connections with a magnifying glass to ensure there are no shorts between pins. Inspect the CF header leads as solder can sometimes flow up the leads during assembly causing a short away from the PCB itself.

=== Bill Of Materials ===

[http://www.farnell.com Farnell] Parts List:

{| class="wikitable" border="1"
|-
!Part(s)
!Description
!Package
!Value
!Qty Required
!Farnell Code
|-
| IC1 || XC9572 72-cell 3.3v CPLD || TQFP100 || - || 1 || 1193233
|-
| IC2 || SST39SF0x0A Flash || TSOP32 (8x14mm) || 1, 2 or 4Mb || 1 || 1829977
|-
| IC3 || SCHMITT TRIG, INV GATE 74LVC1G14 || SOT-25 || - || 1 || 1893833
|-
| VR1 || SPX3819M5-L-3-3 - LDO, 500MA, 3.3V, LOW NOISE || SOT-23-5 || - || 1 || 1831949
|-
| C1 || Low-ESR Electrolytic Capacitor || Radial, 5mm pitch, 10mm max diameter || 47uF to 100uF, 10V+ || 1 || 1692338 (future: SMD 1850100)
|-
| C2, C14 || Ceramic Capacitor (X5R or X7R) || 0805 || 10uF, 10V+ || 2 || 1833812
|-
| C12..13 || Ceramic Capacitor (X5R or X7R) || 0603 || 1uF, 10V+ || 2 || 1828801
|-
| C3..11 || Ceramic Capacitor (X5R or X7R) || 0603 || 0.1uF, 10V+ || 9 || 1414610
|-
| R1..2 || Resistor || 0603 || RESISTOR, 10K, 0.1W || 2 || 1469748
|-
| R3, R5 || Resistor || 0603 || RESISTOR, 1K, 0.1W || 2 || 2008355 or 1652848
|-
| R4 || Resistor || 0603 || RESISTOR, 270R, 0.1W || 1 || 2059585
|-
| R6 || Resistor || 0603 || RESISTOR, 5K6, 0.1W || 1 || 1739171
|-
| RN1, RN2 || Resistor Network || 1206 || RESISTOR NETWORK, 10K, ± 2% || 2 || 1770137
|-
| LED1 || Low-current LED || 0805 || LED, SMD || 1 || 1685055
|-
| DIP_SW || 9-way DIP switch || DIL || SWITCH, DIL, 9WAY || 1 || 1255227
|-
| CF1 || 3M N7E50-Q516 Compact Flash Header || - || 3M N7E50-Q516xx-x0 || 1 || 1267444
|-
| EXT.LED || 2-pin Header || - || HEADER, 1ROW, 2WAY || 1 || 3418285
|-
| JP1 || 3-pin Header || - || HEADER, 1ROW, 3WAY || 1 || 3418297
|-
| JTAG || 6-pin Header || - || HEADER, 2ROW, 6WAY || 1 || 3418492
|-
| - || Jumper for CF Card Voltage Selection || - || - || 1 || 1740370
|}

Notes:

*EXT.LED and R4 can be omited if external activity LED is not required
*LED and R5 can be omited if on-board activity LED is not required
*IC3, R4, R5, LED and EXT.LED can be omited if no activity LEDs are required

== ISA Bracket ==

[[file:peacon-xt-cf-bracket.png|200px|right|thumb|XT-CF Adapter ISA Bracket]]
*ISA Bracket Design per sketch
*To minimise production cost, design has no threaded holes (simple nut-and-bolt required)

== CPLD Logic ==

=== Downloads ===

*[{{SERVER}}/downloads/XT-CF/v1/XT-CFv1-r100-xsvf.zip CPLD XSVF File]
*[{{SERVER}}/downloads/XT-CF/v1/XT-CFv1-r100-ISE-Source.zip CPLD ISE Source Code]

=== Programming the CPLD ===

See [[lo-tech XT-CF CPLD Programming Guide]].

== ROM & BIOS ==

=== ROM ===

*Board design permits the use of [http://www.sst.com/dotAsset/40746.pdf SST39SF0x0A flash chips] (TSOP32, 8x14mm) of 1Mb, 2Mb or 4Mb capacity
*Regardless of the chip used, the first 32KB only will be mapped into the PC address space
*Base address configuration per [[#DIP Switch Settings|DIP Switch Settings]]

=== BIOS ===

*[{{SERVER}}/downloads/XT-CF/xtide-r566-xt-cf-master-slave.zip XT-CF Family BIOS] (configured for 300h)
*The BIOS should be configured using the (BIOS supplied) <tt>xtidecfg.com</tt> utility, then written out to the XT-CF adapter using the [[Lo-tech XT-CF flash utility]]
*For BIOS sources, see the [https://xtideuniversalbios.org/ XTIDE Universal BIOS Site]

== Compatibility and Interoperability ==

=== Use with Other Cards ===

*The IO port address set via the DIP switches must match that set in the XTIDE Universal BIOS configuration utility
*The BIOS address can be changed via the DIP switches without changing the BIOS itself

=== Compatibility ===

*All CompactFlash media can be used. Media supporting multi-sector transfers will provide a performance advantage.
*The adapter can be used in any system supporting 8-bit ISA
*8-bit Port-mapped IO transfer mode is slowest but most compatible
*16-bit Port-mapped IO (BIU offload mode) is not supported on some early PC/XT clones, due to system logic errors
*ROM shadowing will offer significant performance gains on newer hardware, since the flash ROM is 8-bit so BIOS instructions can be fetched much more efficiently from system RAM

== DIP Switch Settings ==

{| class="wikitable" border="1"
!Switch
!Function
!On
!Off
|-
|1 || ROM Enable || Enabled || Disabled
|-
|2 || ROM Base Address || C800h || D000h
|-
|3 || IO Port Address || 300h || 320h
|-
|4** || ISA B8 Enable || Enabled || Disabled
|-
|5** || ISA B8 Function Type (if enabled) || PC-AT (Zero-wait-state) || PC-XT Slot 8
|-
|6* || Not used || - || -
|-
|7* || ISA B8 Output** || - || -
|-
|8* || Not used || - || -
|-
|9 || ROM Write Enable || Enabled || Disabled (ROM cannot be written)
|}

<nowiki>*</nowiki>Switches 6-8 must be OFF. Switch 9 can be left ON, since the flash chip includes Software Data Protection that prevents accidental corruption or overwriting.

<nowiki>**</nowiki>To use the ISA B8 function, wire a jumper from Sw7 resistor-side to ISA B8 pad (see [[:File:XT-CF-ISA-B8-Jumper-Wire.jpg|photo]]).

Default settings: ROM enabled, IO port 300h, ROM base C800h:

{| class="wikitable" border="1"
|-
!1 !!2 !!3 !!4 !!5 !!6 !!7 !!8 !!9
|-
| ON || ON || ON || OFF || OFF || OFF || OFF || OFF || ON
|}

Note that the IO base address is set within the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS] ROM image via the [http://code.google.com/p/xtideuniversalbios/wiki/Manual_v2_0_0#Using_XTIDECFG.COM_(XTIDE_Universal_BIOS_configuration_and_flash Universal BIOS Configuration and Flashing utility]. The IO address set within that utility must much that configured on the card. Should the IO port address be changed for any reason, the BIOS must be updated and re-flashed to the XT-CF card (using the [[lo-tech XT-CF flash utility]]).

The BIOS address is determined at boot time by the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS]. Since the code has been designed to be relocatable, the BIOS base address can be changed without the need to reconfigure the Universal BIOS.

== Known Issues ==

*Activity LED is lit when a CF card isn't inserted. Could be resolved by adding a 50k PU to /PDIAG.
*47uF through-hole capacitor holes are placed too wide (spaced for ~100V capacitors).
*Switch numbers are reversed in the schematic
*ISA B8 isn't connected, hence card cannot be used in slot 8 of IBM PC/XT (see note above)

== See Also ==

*[[Lo-tech XT-CF Boards]]

Lo-tech XT-CFv2 Board

2022-08-17T17:40:27Z

James:

[[File:lo-tech-xt-cfv2-prototype.JPG|right|300px|lo-tech XT-CFv2 Board]]
A development of the [[lo-tech XT-CF Board]], the [[lo-tech XT-CFv2 Board]] has improved functionality and performance, and is slightly cheaper to make.

'''This board was superceded by the [[lo-tech XT-CFv3 Board]], but ultimately these CPLD based cards were discontinued due to lack of CPLD availability. The below content is provided for reference only.'''

== General Description ==

The [[lo-tech XT-CFv2 Board]] is a bootable 8-bit ISA to Compact Flash adapter for XT and AT class IBM compatible PCs. Like the original [[lo-tech XT-CF Board]], the board offers a number of benefits:

*Replace dead MFM or RLL hard disks with a cheap compact-flash card or microdrive
*Easy to access compact-flash card (without opening the PC)
*Reduce system power consumption (and hence load on the PSU) by as much as 30W
*Uses the standard XT-IDE Universal BIOS (adapter type is 'lo-tech XT-CF')
*Increase system performance - offers 5x the throughput of an [[ST-412]]
*32K in-system re-programmable ROM (with 24K free for any other ROM code)

In addition, the [[lo-tech XT-CFv2 Board]] also:

*Can be used in [[IBM Personal Computer XT System Board Slot 8]]
*Has reduced wait-state operation in PC/AT and newer hardware
*Provides the highest possible throughput in PC/XT class hardware via DMA mode operation

== Developments from the [[lo-tech XT-CF Board]] ==

*Added CPLD connections to:
**ISA B8, to support PC/XT slot-8 and PC/AT zero-wait-state operation
**ISA DRQ3, DACK3, and TC, to support DMA transfers via channel 3
**ISA IORDY, to enable bus cycle extension should a CF card require it
**CF header IORDY, as above
*Reduced DIP switch to 8-way an eliminated switchable flash chip write enable line, due to software data-protection mechanisms included in the SST39SF series flash chips
*Changed 47uF capacitor (C1) hole spacing for cheaper 16V capacitors

== Specifications ==

=== General ===

*8-bit ISA card with header for type-I or type-II compact-flash media
*Compact-flash header configured to operate media in true-IDE mode
*500mA 3.3V regulator can drive micro-drives or compact-flash cards without any external power connection (330mA power budget for micro-drives)
*Line driver for on-card and external activity LEDs (30mA power budget for external LED)
*Low-cost SMT Flash memory chip with 32K usable
*JTAG header for CPLD programming

=== Modes of Operation ===

*Port-mapped IO
*Memory-mapped IO
*DMA, via channel 3

Operating mode defaults to port-mapped IO, but can be switched on-the-fly between modes using the [[lo-tech XT-CF Configuration Utility]].

== PCB ==

[[File:Peacon-xt-cfv2-pcb.JPG|right|300px|lo-tech XT-CFv2 PCB]]

=== Boardhouse Requirements ===

*8 mils clearances and minimum track width
*0.4mm minimum hole size
*Can be manufactured on a 100x100mm board
*Gold fingers are preferable but not required

Prototyping is being undertaken using [http://www.seeedstudio.com/depot/fusion-pcb-service-p-835.html SeeedStudio Fusion PCB Service].

=== Assembly Notes ===

*Thoroughly wash the PCB before assembly with Isopropynol
*Place the CF socket, CPLD and flash chip first
*Next place the VRM, LED driver and resistor networks
*Then place LEDs, resistors and SMT capacitors
*Next thoroughly wash the board using a toothbrush to ensure flux is removed from between SMT pins
*Next add the through-hole components (DIP switch, headers and 47uF capacitor), then wash again
*Before use inspect all connections with a magnifying glass to ensure there are no shorts between pins. Inspect the CF header leads as solder can sometimes flow up the leads during assembly causing a short away from the PCB itself.

=== Programming the CPLD ===

See [[lo-tech XT-CF CPLD Programming Guide]].

== ROM & BIOS ==

=== ROM ===

*Board design permits the use of [http://www.sst.com/dotAsset/40746.pdf SST39SF0x0A flash chips] (TSOP32, 8x14mm) of 1Mb, 2Mb or 4Mb capacity
*Regardless of the chip used, the first 32KB only will be mapped into the PC address space
*Base address configuration per [[#DIP Switch Settings|DIP Switch Settings]]

=== BIOS ===

This card was supported by the [[XTIDE Universal BIOS]].

== Bill Of Materials ==

[http://www.farnell.com Farnell] Parts List:

{| class="wikitable" border="1"
|-
!Part(s)
!Description
!Package
!Value
!Qty Required
!Farnell Code
|-
| IC1 || XC9572 72-cell 3.3v CPLD || TQFP100 || - || 1 || 1193233
|-
| IC2 || SST39SF0x0A Flash || TSOP32 (8x14mm) || 1, 2 or 4Mb || 1 || 1829977
|-
| IC3 || SCHMITT TRIG, INV GATE 74LVC1G14 || SOT-25 || - || 1 || 1893833
|-
| VR1 || SPX3819M5-L-3-3 - LDO, 500MA, 3.3V, LOW NOISE || SOT-23-5 || - || 1 || 1831949
|-
| C1 || Electrolytic Capacitor || Radial, 2mm pitch, 5mm diameter || 47uF to 100uF, 10V+ || 1 || 8767114
|-
| C2, C14 || Ceramic Capacitor (X5R or X7R) || 0805 || 10uF, 10V+ || 2 || 1833812
|-
| C12..13 || Ceramic Capacitor (X5R or X7R) || 0603 || 1uF, 10V+ || 2 || 1828801
|-
| C3..11 || Ceramic Capacitor (X5R or X7R) || 0603 || 0.1uF, 10V+ || 9 || 1414610
|-
| R2 || Resistor || 0603 || RESISTOR, 10K, 0.1W || 1 || 1469748
|-
| R3, R5 || Resistor || 0603 || RESISTOR, 1K, 0.1W || 2 || 2008355 or 1652848
|-
| R4 || Resistor || 0603 || RESISTOR, 270R, 0.1W || 1 || 2059585
|-
| R6 || Resistor || 0603 || RESISTOR, 5K6, 0.1W || 1 || 1739171
|-
| RN1, RN2 || Resistor Network || 1206 || RESISTOR NETWORK, 10K, ± 2% || 2 || 1770137
|-
| LED1 || Low-current LED || 0805 || LED, SMD || 1 || 1685055
|-
| SW1 || 8-way DIP switch || DIL || SWITCH, DIL, 8WAY || 1 || 9471596
|-
| CF1 || 3M N7E50-Q516 Compact Flash Header || - || 3M N7E50-Q516xx-x0 || 1 || 1267444
|-
| EXT.LED || 2-pin Header || - || HEADER, 1ROW, 2WAY || 1 || 3418285
|-
| JP1 || 3-pin Header || - || HEADER, 1ROW, 3WAY || 1 || 3418297
|-
| JTAG || 6-pin Header || - || HEADER, 2ROW, 6WAY || 1 || 3418492
|-
| - || Jumper for CF Card Voltage Selection || - || - || 1 || 1740370
|}

Notes:

*EXT.LED and R4 can be omited if external activity LED is not required
*LED and R5 can be omited if on-board activity LED is not required
*IC3, R4, R5, LED and EXT.LED can be omited if no activity LEDs are required
*There is no 'R1'

== ISA Bracket ==

[[file:peacon-xt-cf-bracket.png|200px|right|thumb|XT-CF Adapter ISA Bracket]]
*ISA Bracket Design per sketch
*To minimise production cost, design has no threaded holes (simple nut-and-bolt required)
*Production likely to also exclude bending
*CAM Files: (in development)

== Compatibility and Interoperability ==

=== Use with Other Cards ===

*The card can be configured to use DMA Ch.3 or not to - see [[XT-CFv2#DIP_Switch_Settings|DIP Switch Settings]]
*The IO port address set via the DIP switches must match that set in the XTIDE Universal BIOS configuration utility
*The BIOS address can be changed via the DIP switches without changing the BIOS itself

=== Media Compatibility ===

{|class="wikitable"
!Media
!Type
!Capacity
!At 3.3V
!At 5V
!Tester
|-
| Extreme CF Adapter || SD to Type II CF Adapter || Dependent on SD Card || - || - || -
|-
| Kingston CF/128 || CF || 128MB || - || - || -
|-
| PQI Industrial || CF || 1 GB || - || - || -
|-
| SanDisk Ultra II || CF || 2 GB || - || - || -
|-
| SanDisk Ultra (30MB/s) || CF || 4 GB || - || - || -
|-
| Seagate ST1 || Microdrive || 5 GB || - || - || -
|-
| VERBATIM 44039 || CF || 4 GB || - || - || -
|}

=== Systems Compatibility ===

System compatibility has determined using the [[DOS Disk Tester]] utility with a pattern test of at least 10 passes of 4MB (the default).

{|class="wikitable"
!System
!CPU
!Status
!Disk Tester Version
!Tester
|-
| [[IBM Personal Computer 5150|IBM PC 5150]] || [[Intel 8088]] || - || 2.3 || -
|-
| [[IBM Portable Computer 5155|IBM Portable PC 5155]] || [[Intel 8088]] || - || 2.3 || -
|-
| [[IBM Personal Computer XT 5160|IBM PC/XT 5160]] || [[NEC V20]] || - || 2.3 || -
|-
| Chaintech 5SIM || IDT WinChip P200 || - || 2.3 || -
|}

== Performance ==

=== Factors Affecting Performance ===

*The host CPU speed
*The system type (PC/XT vs PC/AT)
*For PC/AT and newer systems, whether the BIOS can be shadowed in system RAM or not
*The operating mode (IO-mapped, memory-mapped or DMA)
*The multi-sector transfer support in the media

Many Compact Flash cards support only single-sector transfers, which results in increased BIOS overhead, particularly in DMA transfer mode (since the DMA controller must be programmed for each sector).

=== General Performance Notes ===

*IO-mapped transfer mode is slowest on all platforms but needs the least resources and has the best compatibility
*Memory-mapped transfer mode (enabled once DOS has booted with the [[lo-tech XT-CF Configuration Utility]]) offers increased performance but needs a 4KB transfer block available, for example at D800h.
**On PC/AT and newer systems, this (combined with ZWS configuration) will offer highest throughput
**This mode makes use of the bus interface logic by using 16-bit instructions (<tt>rep movsw</tt>), and therefore depends on proper implementation of that logic to work (some machines may not support this mode)
*DMA transfer mode (enabled once DOS has booted with the [[lo-tech XT-CF Configuration Utility]]) is fastest on PC/XT class hardware, but needs DMA Ch.3 available, so cannot be used if another device is using DMA Ch.3 (such as an MFM disk controller)
*ROM shadowing will offer significant performance gains on newer hardware, since the flash ROM is both 8-bit and ISA bus speed limited (BIOS code will be fetched much more efficiently from system RAM)

=== Sample System Measured Throughput ===

{|class="wikitable"
!System !!CPU !!Transfer Mode !!Media type !!Throughput
|-
|IBM PC/XT ||4.77MHz 8088 ||IO-mapped ||CF card supporting single-sector transfers ||150KB/s
|-
|IBM PC/XT ||4.77MHz 8088 ||DMA ||CF card supporting multi-sector transfers ||500KB/s
|-
|Amstrad PC2086 ||12.5MHz 80286 ||Memory-mapped ZWS ||CF card supporting multi-sector transfers ||1MB/s
|-
|Generic Pentium ||200MHz Pentium ||Memory-mapped ZWS ||CF card supporting multi-sector transfers ||1.6MB/s
|}

== DIP Switch Settings ==

{| class="wikitable" border="1"
!Switch
!Function
!On
!Off
|-
|1 || IO Port A8 || 1 || 0
|-
|2 || IO Port A6 || 1 || 0
|-
|3 || ISA B8 / DMA Functions || ISA B8 Enabled || DMA Ch.3 Enabled
|-
|4 || ISA B8 Function Type (if enabled) || PC-AT (Zero-wait-state) || PC-XT Slot 8
|-
|5 || ROM A17 || 1 || 0
|-
|6 || ROM A16 || 1 || 0
|-
|7 || ROM A15 || 1 || 0
|-
|8 || ROM Enable || Enabled || Disabled
|}

Default settings are:

*IO port 300h
*DMA Operation Enabled and ISA B8 function disabled
*ROM base address D000h
*ROM enabled

{| class="wikitable" border="1"
|-
!1 !!2 !!3 !!4 !!5 !!6 !!7 !!8
|-
|ON || OFF || OFF || OFF || OFF || ON || OFF || ON
|}

=== IO Range ===

{| class="wikitable" border="1"
!IO Port Base Address
!Sw1
!Sw2
|-
|200h || OFF || OFF
|-
|240h || OFF || ON
|-
|300h (Default) || ON || OFF
|-
|340h || ON || ON
|}

Note that the IO base address is set within the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS] ROM image via the [http://code.google.com/p/xtideuniversalbios/wiki/Manual_v2_0_0#Using_XTIDECFG.COM_(XTIDE_Universal_BIOS_configuration_and_flash Universal BIOS Configuration and Flashing utility]. The IO address set within that utility must much that configured on the card via switches 1 and 2. Should the IO port address be changed for any reason, the BIOS must be updated and re-flashed to the XT-CFv2 card (using the [[lo-tech XT-CF flash utility]]).

=== ROM Base Address ===

{| class="wikitable" border="1"
!ROM Base Address
!Sw5
!Sw6
!Sw7
|-
|C000h || OFF || OFF || OFF
|-
|C800h || OFF || OFF || ON
|-
|D000h (Default) || OFF || ON || OFF
|-
|D800h || OFF || ON || ON
|-
|E000h || ON || OFF || OFF
|-
|E800h || ON || OFF || ON
|}

The BIOS address is determined at boot time by the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS]. Since the code has been designed to be relocatable, the BIOS base address can be changed with switches 5-7 without the need to reconfigure the Universal BIOS.

Note that the BIOS base address is not related to the memory-mapped IO transfer address, except that the two ranges cannot overlap - see the [[lo-tech XT-CF Configuration Utility]].

=== ISA B8 and DMA Function ===

ISA B8 in the PC/XT [[IBM Personal Computer XT System Board Slot 8|was used as a card select line to read from a card physically in the ISA slot closest to the CPU (known as slot 8)]], and has no function in other slots in the PC/XT. Preliminary research has shown that it's also unconnected in PC/XT clones (including, for example, the Tandy 1000TL despite that being an [[Intel 80286]] based machine). In PC/AT and above, the line was used instead to shorten card access cycles by eliminating wait-states.

The logic design of the PC/XT system board prevents DMA transfers being performed from slot 8, so slot 8 function and DMA are mutually exclusive. Also note that memory-mapped transfers, that benefit from reduced wait states, are faster for PC/AT class hardware. Therefore, switch 3 switches between DMA or slot 8 / reduced wait states.

However, for the XT-CFv2 card to co-exist in a system with an MFM controller or other device that requires DMA Ch.3, DMA must be disabled by setting switch 3 to ON. The card doesn't though need to be in slot 8, since the line serves no purpose in the other slots.

Sample switch positions:

{|class="wikitable"
!Card Placement !! DMA function !! Sw3 !! Sw4
|-
|PC/XT or clone || Enabled || OFF || OFF
|-
|PC/XT or clone || Disabled || ON || OFF
|-
|PC/XT slot-8 || Disabled || ON || OFF
|-
|PC/AT or newer || Disabled || ON || ON
|}

== Known Issues ==

*Activity LED is lit when a CF card isn't inserted. Could be resolved by adding a 50k PU to /PDIAG.

== See Also ==

*[[XT-IDE]]

Lo-tech XT-CFv3 Board

2022-08-17T17:38:25Z

James: Redirected page to XT-CFv3

#REDIRECT [[XT-CFv3]]

Lo-tech XT-CF Board Technical Reference

2022-08-17T17:36:36Z

James:

Technical Reference manual for the [[lo-tech XT-CF Board]].

== CPLD Code Design ==

The CPLD code has been developed using Xilinx ISE version 13, using schematics, for the XC9572XL CPLD device. The starting point was the code generated by Dangerous Prototypes forum member Pietja, for use with the [[Dangerous_Prototypes_XT-IDE_Boards#Version_2|Dangerous Prototypes XT/IDE v2 board]].

=== ROM_DECODER Module ===

The ROM decoder matches the PC address bus against the configuration of appropriate DIP switches, providing an asserted (low) signal output when a match is found, that signal being used to enabled the board ROM. It is a direct transcription of a 74521 or 74688 chip, output being disabled when AEN is asserted.

Once enabled, data is transferred from the ROM itself under the control of /MEMR and /MEMW and the low 14-bits of the PC address bus.

=== IDE_DECODER Module ===

The IDE decoder matches the PC address bus against two address locations:

*For port-based IO, A5..8 are matched to the configuration set by the DIP switches on the board (by default, base is 300h), A9 being high and A19 being low
*For memory-mapped IO, A12..19 (the upper 8 bits) are matched to the value stored in the memory-mapped IO register (a latch), output being asserted also only if A19 in the latch has been set to 1. A10 and A11 must also be low.
*In both cases, AEN suppresses output when asserted.

If either are matched, CS_IDE is asserted (low). Additionally, CS_IDE_MEM is asserted (low) if the memory-mapped IO address is matched.

Other outputs generate control information, for example to enable the IDE_MUX to provide the controller ID byte when a read to the controller ID port is made.

The decoder also provides mapping of PC address bus lines to the IDE interface address lines, DA0..2, according to the '[http://www.vintage-computer.com/vcforum/showthread.php?23971 Chuck Mod]' logic, whereby IDE DA0 is connected to PC address bus A3 (instead of A0, as might be expected):

{|class="wikitable"
!PC Address Line !!IDE Address Line
|-
|A0 || -
|-
|A1 || DA1
|-
|A2 || DA2
|-
|A3 || DA0
|}

This presentation leaves A0 free to be used to switch between low and high bytes of each 16-bit word, thereby enabling faster transfers via word instructions. Otherwise, for example if A3 were used to switch bytes, individual byte transfers and XOR instructions with a bit-mask would be needed, which reduces throughput (significantly).

Note that when CS_IDE is asserted based on memory-mapped IO address match, DA0..2 are held low; because of this the memory-mapped function can be used only for sector data transfers.

=== IDE_MUX Module ===

The IDE mux module provides the interface between the 8-bit PC bus, PCBD(7:0), and the 16-bit IDE bus, presented in two 8-bit components as IDE_DH(7:0) and IDE_DL(7:0). The mux works by storing a byte in a latch when required, then subsequently presenting that byte either to the PC data bus (for reads) or the IDE interface (for writes, concurrently with the data from the PC data bus to make up the required 16-bits).

The mux component also provides the logic to present the device ID byte (via port Base+0Fh) and a latch that can be loaded with the memory-mapped IO base address (also via port Base+0Fh).

The mux is enabled by IDE_DECODER module output CS_IDE, being asserted if either memory-mapped or port-mapped addresses match the configured ranges.

Since IO operations are addressed by A0..A9 and memory operations are addressed with A0..A19, use of the /MEMR and /MEMW signals (for memory-mapped IO) must be checked against the memory mapped base address specifically (given by CS_IDE_MEM). Without this check, a memory read matching the IO port range in A0..A9 could trigger some IDE function. The reverse test is not necessary for /IOR and /IOW, since A10..A19 will always be low during IO operation, hence the CS_IDE_MEM signal could not be asserted concurrently.

== Port Based IO ==

The base port address (Base) is configured via the [[lo-tech_XT-CF_Board#DIP_Switch_Settings|DIP switches]]. Since the logic uses A0..A4, 32 consecutive ports are used (Base+00h to Base+1Fh).

{|class="wikitable"
!Base+ !! Function
|-
|00h || Sector transfer (read low-byte)
|-
|01h || Sector transfer (read high-byte)
|-
|02h to 0Eh || IDE functions (note address line mapping)
|-
|0Fh || Read controller ID byte or set memory-mapped IO base address
|-
|10h || Sector transfer (write low-byte)
|-
|11h || Sector transfer (write high-byte)
|-
|12h to 1Fh || IDE control register access (note address line mapping)
|}

The controller uses A0 to determine if the low or high order byte is being transferred, and A4 to determine if the operation is read or write:

*For reads, A0 inverts IDE /CS0 and /CS1, such that the read command is driven on to the IDE bus only when accessing port Base+00h. When A0 is asserted, the two CS lines are switched, the three IDE lines DA0..2 remaining low, yielding a no-op as viewed by the IDE device. This allows the high order byte to be transferred from the latch to the PC data bus.
*For writes, the operation of the IDE /CS0 and /CS1 inversion based on A0 is itself inverted by A3 being asserted. That is, the IDE device sees the write to port Base+10h as a no-op, allowing the low order byte to be stored in the latch, and the write to port Base+11h as a valid write. The IDE word write will consist of IDE_DL(7:0), being presented from the latch, and IDE_DH(7:0), being presented from the byte on the PC data bus.

Controller specific functions:

*Reading from port Base+0Fh returns the controller ID byte, a fixed value coded into the CPLD logic:
**03h = Port-based 'enhanced' operation (word-transfer logic)
**04h = As type 03h, but also with memory-mapped CPLD logic
**The original board and the 'standard' CPLD code do not return a specific value from this port
*Memory-mapped IO is enabled by setting the high 8-bits of the required memory-mapped base address via writing to port Base+0Fh, and disabled by writing a value of 0 to the same port. The function is disabled at power-up, and can be enabled and disabled on-the-fly.

== Memory Mapped IO ==

Memory mapped IO is a method of transferring data from a device as though it were system memory (so using A0..19 and /MEMR and /MEMW signals, instead of the /IOR and /IOW signals used for port-based IO). This technique offers a performance advantange on the 8088 CPU, since <tt>rep movsw</tt> can be used (25 cycles/word) instead of seperate load, store and loop instructions (30 to 48 cycles/word, depending on loop unrolling). (Note that 8-bit ISA bus timing is the same for both methods.)

IDE control and enquiry functions are always completed through the IO ports as detailed above, but sector data can be transferred by either port-based or memory-mapped IO (provided the controller ID port returns 04h).

To enable memory-mapped IO, the high 8-bits of the required memory-mapped base address are loaded through port Base+0Fh, noting that the MSB must be asserted. The card will then enable transfers through that base address in two ranges within a 4KB aligned 1KB block:

{|class="wikitable"
!Base+ !! Function
|-
|0000h to 01FFh || Read window
|-
|0200h to 03FFh || Write window
|}

Only the transfer of sector data can be performed; IDE DA0..DA2 are held low during such IO. The transfer must be made in asceding sequence since words will be committed to (or read from) the IDE interface synchronously (the card buffer is only one byte, in the IDE_MUX module).

*As with port-based IO, the controller uses A0 to determine if the low or high byte is being transferred
*A9 is used to determine if the operation is read or write
*A1..A8 are not monitored, allowing the CPU to cycle though the 512 bytes in asceding order starting at zero, using <tt>rep movsw</tt>

For example, if the IO transfer window is to be D800:0000, send D8h to port Base+0Fh. Data can then be read from D800:0000-01FF, or written to D800:0200-03FF.

Once the transfer has been completed, memory-mapped IO function can be disabled by writing zero to port Base+0Fh. Note that port-based IO can be used regardless of whether memory-mapped IO is enabled or not.

== Programming Examples ==

The following code examples illustrate block-mode transfers (i.e. of 1 to 128 sectors) for either port-mapped or memory-mapped controllers. For the sake of simplicity, the memory-mapped base address is hard-coded where required.

=== Block Read Example ===

<source lang="asm">
; Block read routine, with memory-mapped IO if supported
; On-entry:
; DX : IDE controller base port (low 4-bits always zero)
; CX : sector count (max 128)
; ES:DI : target memory buffer address
;
; Corrupts: AX, CX, DX

or dl, 0x0f ; set DX to conntroller ID port (base+0Fh)
in al, dx ; get controller type
cmp al, 4 ; 4 = memory-mapped capable
jne .PortBasedRead ; use port-based IO if not type 4
mov al, 0xd8 ; set AL to high 8-bits of mem-mapped IO base...
out dx, al ; ... send high 8-bits of segment address to controller ID port ...
xor ah, ah ; ... and clear AH ...
xchg al, ah ; ... and swap AL/AH - AX now contains base address for reads
push ds ;
push si ; save DS:SI
mov ds, ax ; move segment address in AX to DS
mov ax, cx ; store total sector count in AX
xor cx, cx ; clear CX
.ReadTransferLoop: ; sector-by-sector transfer loop (256 words each iteration)
; note CX is zero at start of each iteration
mov si, cx ; clear SI; DS:SI now has mem-mapped IO base address
inc ch ; memory-mapped window is 512 bytes, CX now has 256 (words)
rep movsw ; do the transfer from [DS:SI] to [ES:DI], count in CX (256)
dec ax ; reduce number of sectors still to get
jnz .ReadTransferLoop ; repeat, if there's more to do (zero flag set by dec)
out dx, al ; we're done; disable memory-mapped IO (AL will be zero)
pop si
pop ds ; restore register values
ret
.PortBasedRead:
xchg cl, ch ; Sectors to words (SHL 8)
and dl, 0xf0 ; restore value in DX (the read IO port)
shr cx, 1 ;
shr cx, 1 ;
shr cx, 1 ; words to octa-words (16 bytes - shr 3)
.ReadNextOctaword: ; port-based IO code follows, unrolling improves throughput
in ax, dx ; Read 1st word
stosw ; Store 1st word to [ES:DI]
in ax, dx
stosw ; 2nd
in ax, dx
stosw ; 3rd
in ax, dx
stosw ; 4th
in ax, dx ;
stosw ; 5th
in ax, dx
stosw ; 6th
in ax, dx
stosw ; 7th
in ax, dx
stosw ; 8th
loop .ReadNextOctaword ; 17 clocks on 8088 hence unrolling
ret
</source>

=== Block Write Example ===

<source lang="asm">
; Block write routine, with memory-mapped IO if supported
; On-entry:
; DX : IDE controller base port (low 4-bits always zero)
; CX : sector count (max 128)
; ES:SI : source memory buffer address
;
; Corrupts: AX, CX, DX

push ds ; save DS
mov ax, es ;
mov ds, ax ; move ES to DS via AX; DS:SI now pointer to source memory buffer
or dl, 0x0f ; set DX to conntroller ID port (base+0Fh)
in al, dx ; get controller type
cmp al, 4 ; 4 = memory-mapped capable
jne .PortBasedWrite ; use port-based IO if not type 4
mov al, 0xd8 ; set AL to high 8-bits of mem-mapped IO base...
out dx, al ; ,.. send high 8-bits of segment address to controller ID port ...
mov ah, al ; ... mov AL to AH ...
mov al, 0x20 ; ... and set AL to write offset. AX now contains write base address
push es ;
push di ; save ES:DI
mov es, ax ; move segment address in AX to ES
mov ax, cx ; store total word count in AX
xor cx, cx ; clear CX
.WriteTransferLoop: ; sector-by-sector transfer loop (256 words each iteration)
; note CX is zero at start of each iteration
mov di, cx ; clear DI - ES:DI now has mem-mapped IO write base address
inc ch ; memory-mapped window is 512 bytes, CX now has 256 (words)
rep movsw ; do the transfer from [DS:SI] to [ES:DI], count in CX (256)
dec ax ; reduce number of sectors still to write
jnz .WriteTransferLoop ; repeat, if there's more to do (zero flag set by dec)
out dx, al ; disable memory-mapped IO (AL will be 0)
pop di ;
pop es ;
pop ds ; restore register values
ret
.PortBasedWrite: ; Port-based IO routine follows
xchg cl, ch ; Sectors to words (SHL 8)
shr cx, 1 ;
shr cx, 1 ;
shr cx, 1 ; words to octa-words (16 bytes - shr 3)
xor dl, 0x1f ; restore value in DX to Base+10h
.WriteNextOctaword: ; port-based IO code follows, unrolling improves throughput
lodsw ; Load 1st word from [DS:SI]
out dx, ax ; Write 1st word
lodsw
out dx, ax ; 2nd
lodsw
out dx, ax ; 3rd
lodsw
out dx, ax ; 4th
lodsw ;
out dx, ax ; 5th
lodsw
out dx, ax ; 6th
lodsw
out dx, ax ; 7th
lodsw
out dx, ax ; 8th
loop .WriteNextOctaword ; 17 clocks on 8088, hence unrolling
pop ds ; restore DS to entry state
ret
</source>

== See Also ==

*[[lo-tech XT-CF Board]]

Tandy 1400 Series Expansion Slots

2022-08-17T17:35:28Z

James: /* Expansion Slot */

[[Tandy 1400 Series Laptops]] included a two expansion slots on a riser card under the right-hand drive bay:

*Expansion slot - all variants
*Memory Expansion slot - [[Tandy 1400LT]]
*Hard Disk Controller slot - [[Tandy 1400FD]] and [[Tandy 1400HD]]

The memory fitted to the memory expansion slot in the 1400LT was included on the FD/HD motherboard - all machines had 768KB RAM.

== Expansion Slot ==

=== Mechanical Drawing ===

From the [{{SERVER}}/downloads/manuals/tandy/Tandy_1400LT_Service_Manual.pdf 1400LT Service Manual] (page 4-66):

[[file:Tandy-1400-Expansion-Slot-PCB-Mechanical-Drawing.png]]

=== Pinout ===

{|class="wikitable"
!Pin !!Signal !!Notes
|-
| P1 || N/C || -
|-
| P2 || 5V || 200mA max
|-
| P3 || /ENABLE || -
|-
| P4 || N/C || -
|-
| P5 || N/C || -
|-
| P6 || /DACK0 || System RAM refresh
|-
| P7 || IRQ3 || -
|-
| P8 || N/C || -
|-
| P9 || GND || -
|-
| P10 || A0 || -
|-
| P11 || A1 || -
|-
| P12 || A2 || -
|-
| P13 || A3 || -
|-
| P14 || A4 || -
|-
| P15 || A5 || -
|-
| P16 || A6 || -
|-
| P17 || A7 || -
|-
| P18 || GND || -
|-
| P19 || A8 || -
|-
| P20 || A9 || -
|-
| P21 || A10 || -
|-
| P22 || A11 || -
|-
| P23 || A12 || -
|-
| P24 || A13 || -
|-
| P25 || A14 || -
|-
| P26 || A15 || -
|-
| P27 || GND || -
|-
| P28 || A16 || -
|-
| P29 || A17 || -
|-
| P30 || A18 || -
|-
| P31 || A19 || -
|-
| P32 || D0 || -
|-
| P33 || D1 || -
|-
| P34 || D2 || -
|-
| P35 || D3 || -
|-
| P36 || GND || -
|-
| P37 || D4 || -
|-
| P38 || D5 || -
|-
| P39 || D6 || -
|-
| P40 || D7 || -
|-
| P41 || /EMW || -
|-
| P42 || /EMR || -
|-
| P43 || GND || -
|-
| P44 || /EIW || -
|-
| P45 || /EIR || -
|-
| P46 || /TC || Active low (opposite to ISA bus)
|-
| P47 || ALE || -
|-
| P48 || /BRST || Active low (opposite to ISA bus)
|-
| P49 || /DACK1 || -
|-
| P50 || IRQ2 || -
|-
| P51 || GND || -
|-
| P52 || 5V || 200mA max
|-
| P53 || ECLK || 50% duty cycle CPU clock
|-
| P54 || IRQ5 || -
|-
| P55 || DRQ3 || -
|-
| P56 || /DACK3 || -
|-
| P57 || BEN || -
|-
| P58 || DRQ1 || -
|-
| P59 || IOREADY || -
|-
| P60 || N/C || -
|}

== See Also ==

*[[CompactFlash Adapter for Tandy 1400 Laptops]]
*[[Tandy 1400 Series Laptops]]

Dangerous Prototypes XT-IDE Boards

2022-08-17T17:34:55Z

James: /* Resources */

The Dangerous Prototypes 'V1' boards took the [[Vintage-Computer XT-IDE Board | original XT-IDE design]] and ported some of the functionality into a small [http://www.xilinx.com/support/documentation/data_sheets/DS063.pdf Xilinx 9500 series CPLD]. Because of short supply of 5V parts, the design was modified to use a 3.3V CPLD experimentally, and after successful testing of this the design was then ported to an entirely 3.3V CPLD based implementation with the V2.

The CPLD reduces the component count (and hence cost), but many home assemblers are likely to be put off by the SMT components, although they are manageable with [[SMT Soldering Notes|only basic tools]].

== BIOS ==

Any of the standard [[XT-IDE#BIOS |XT-IDE BIOS's]] can be used. Testing has been performed using the [http://code.google.com/p/xtideuniversalbios/ XTIDE universal BIOS], V1.15.

== Varients ==

*V1 - XC9572 CPLD with some 74LS series ICs, all SMT
*V1a - Revised to use XC9572XL (3.3V); has errors
*V1b - Corrected V1a; works well
*V2 - TQFP-100 XC9572XL CPLD with no other ICs. See [[Dangerous Prototypes V2 Compatibility Notes]]

== Resources ==

*[http://dangerousprototypes.com/docs/XT_IDE_disk_controller Project Home Page]
*[http://dangerous-prototypes-open-hardware.googlecode.com/svn/trunk/XTIDE_CPLD/ Code Repository]

== Version 1 ==

*The original cersion was never built, since the 5V XC9572 was discontinued before the board was finished
*The v1 board was made, but wasn't cut correctly
*The v1a board has a number of design errors, including 5 missing traces
*The v1b board is sound. When constructed, a minor change to the CSEL header pin (pin 28) should be made to ensure drive compatibility.

=== v1a ===

[[file:dp-xtide-v1a.jpg|300px|right]]
[http://www.farnell.com Farnell] BoM:

{| class="wikitable" border="1"
|-
!Part(s)
!Description
!Package
!Value
!Qty Required
!Farnell Code
|-
| C1,C3,C4,C5,C7 || Ceramic Capacitor || C 0603 || 0.1uF || 5 || 1833863
|-
| C2 || Ceramic Capacitor || Case C || 47uF || 1 || 9695664
|-
| C6 || Ceramic Capacitor || C 0603 || 1uF || 10 || 1828801
|-
| DIP_SW || 8-way DIP switch || DIL || SWITCH, DIL, 8WAY || 1 || 9471596
|-
| IC Socket || IC Socket || DIP-28 || SOCKET IC, DIL, 28WAY || 1 || 1077330
|-
| IC1 || EEPROM (64k as 8K x8) || DIL-28 || 28C64 || 1 || 1095784
|-
| IC2 || 74HC688DW || SOIC-20 || 74HC688DW || 1 || 1740268
|-
| IC3, IC4 || 74HCT573D || SOIC-20 || 74HCT573D || 2 || 1201309
|-
| IC5 || 74HCT245DW || SOIC-20 || 74HCT245DW || 1 || 9591923
|-
| IC6 || XC9572 72-cell 3.3v CPLD || VQ44 || XC9572XL-10VQG44C || 1 || 1605849
|-
| IDE1 || 40-pin IDE Header || MA20-2 || HEADER, 2.54MM, BOXED, 2X20WAY || 1 || 8395977
|-
| JP1, JP2, JP3, JP7 || 16-pin Jumper Header (cut for each) || 2.54mm pitch || HEADER, 2ROW, 16WAY || 1 || 3418546
|-
| JP4 || 3-pin Jumper Header || 2.54mm pitch || HEADER, 1ROW, 3WAY || 1 || 3417657
|-
| JP6 || 6-pin Jumper Header || 2.54mm pitch || HEADER, 1ROW, 6WAY || 1 || 1187827
|-
| LED1 || Activity LED || 0805 || LED, SMD, RED || 1 || 1226389
|-
| R1,R2,R3,R4,R5,R6,R7 || Resistor || 0603 || RESISTOR, 10KR, 0.1W, 5% || 7 || 1469749
|-
| RN1, RN2 || Resistor Network || SIL9 || RESISTOR NETWORK, 10K, ± 2% || 2 || 9356819
|-
| VR1 || Voltage Regulator || SOT-23-5 || MIC5205-3.3YM5 || 1 || 1663083
|}

=== v1b ===

[[file:dp-xtide-v1b.jpg|300px|right]]
Enhancements over v1a:

*Missing traces fixed
*Seperate resistor for on-board and header-attached activity LED
*Jumper to enable 5V CPLD to be used
*Jumper header to enable connection of IDE Pin 20 to VCC for Disk-On-Module use
*SMT resistor networks

[http://www.farnell.com Farnell] BoM:

{| class="wikitable" border="1"
|-
!Part(s)
!Description
!Package
!Value
!Qty Required
!Farnell Code
|-
| C1,C3,C4,C5,C7 || Ceramic Capacitor || C 0603 || 0.1uF || 5 || 1833863
|-
| C2 || Electrolytic Capacitor || Case C || 47uF || 1 || 1973276
|-
| C6 || Ceramic Capacitor || C 0603 || 1uF || 1 || 1828801
|-
| DIP_SW || 8-way DIP switch || DIL || SWITCH, DIL, 8WAY || 1 || 9471596
|-
| IC Socket || IC Socket || DIP-28 || SOCKET IC, DIL, 28WAY || 1 || 1077330 or 1103852
|-
| IC1 || EEPROM (64k as 8K x8) || DIL-28 || 28C64 || 1 || 1095784
|-
| IC2 || 74HC688DW || SOIC-20 || 74HC688DW || 1 || 1740268
|-
| IC3, IC4 || 74HCT573D || SOIC-20 || 74HCT573D || 2 || 9592083
|-
| IC5 || 74HCT245DW || SOIC-20 || 74HCT245DW || 1 || 9591923
|-
| IC6 || XC9572 72-cell 3.3v CPLD || VQ44 || XC9572XL-10VQG44C || 1 || 1605849
|-
| IDE1 || 40-pin IDE Header || MA20-2 || HEADER 40WAY || 1 || 1099261
|-
| JP1, JP2, JP5, JP6, JP7 || Jumper Header (cut for each) || 2.54mm pitch || HEADER, 1ROW, 14WAY || 1 || 3418376 (10-pin) 3418303 (4-pin)
|-
| LED1 || Activity LED || 0805 || LED, SMD, RED || 1 || 1226389
|-
| R1,R2,R3,R4,R5, R7,R8,R9,R10 || Resistor || 0603 || RESISTOR, 10KR, 0.1W, 5% || 9 || 1469749
|-
| RN1, RN2 || Resistor Network || 0603 || RESISTOR NETWORK, 10K, ± 2% || 2 || 2060107
|-
| VR1 || Voltage Regulator || SOT-23-5 || MIC5205-3.3YM5 || 1 || 1663083
|-
| - || Jumpers || - || - || 2 || 1740370
|-
| - || ISA Bracket || - || Keystone 9202 || 1 || 4567699
|-
| - || Panhead screws || - || SCREW MACHINE PHILLIPS 4-40X1/4 || 2 || -
|}

Notes:

*JP4 and R6 aren't required; short IDE header pins 28 and 30
*JP5 is needed only if a Disk-On-Module is likely to be used (to provide power via the header)
*JP3 (IRQ) is not needed
*R7 and the LED1 are needed only if activity indication on-board is required
*R10 and associated 2-pin header JP7 are needed only if remote activity indication is required
*SJ1 should be soldered closed if a 5V CPLD is used, otherwise left open

== Version 2 ==

[[file:dp-xtide-v2.jpg|300px|right]]
The version 2 board is a sound design, with no modifications needed during construction.

[http://www.farnell.com Farnell] BoM:

{| class="wikitable" border="1"
|-
!Part(s)
!Description
!Package
!Value
!Qty Required
!Farnell Code
|-
| C1,C3..4,C7..11 || Ceramic Capacitor X7R || 0603 || 0.1uF || 8 || 1759123
|-
| C2 || Electrolytic Capacitor || Case C || 47uF || 1 || 1973276
|-
| C6 || Ceramic Capacitor || 0603 || 1uF || 1 || 1833809
|-
| DIP_SW || 8-way DIP switch || DIL || SWITCH, DIL, 8WAY || 1 || 9471596
|-
| IC Socket || IC Socket || DIP-28 || SOCKET IC, DIL, 28WAY || 1 || 1103852
|-
| IC1 || EEPROM (64k as 8K x8) || DIL-28 || 28C64 || 1 || 1095784
|-
| IC7 || XC9572 72-cell 3.3v CPLD || TQFP100 || XC9572XL || 1 || 1193233
|-
| IDE1 || 40-pin IDE Header || MA20-2 || HEADER 40WAY || 1 || 1099261
|-
| JP1, JP2, JP6 || Jumper Header (cut for each) || 2.54mm pitch || HEADER, 1ROW, 10WAY || 1 || 3418376
|-
| LED1 || Activity LED || 0805 || LED, SMD, RED || 1 || 1686066
|-
| R2..4 || Resistor || 0603 || RESISTOR, 10KR, 0.1W, 5% || 3 || 2008360
|-
| R6, R7 || Resistor || 0603 || RESISTOR, 270R, 0.1W, 1%, 250mW || 2 || 1738897
|-
| RN3, RN4 || Resistor Network || 1206 || RESISTOR ARRAY, 10K || 2 || 1770137
|-
| VR1 || Voltage Regulator || SOT-23-5 || MIC5205-3.3YM5 || 1 || 1663083
|-
| - || Jumpers || - || - || 2 || 1740370
|-
| - || ISA Bracket || - || Keystone 9202 || 1 || 4567699
|-
| - || Panhead screws || - || SCREW MACHINE PHILLIPS 4-40X1/4 || 2 || -
|}

Notes:

*JP5 is needed only if a Disk-On-Module is likely to be used (to provide power via the header)
*JP3 (IRQ) is not needed
*R7 and the LED1 are needed only if activity indication on-board is required
*R10 and associated 2-pin header JP7 are needed only if remote activity indication is required

== See Also ==

*[[Dangerous Prototypes V2 Compatibility Notes]]
*[[XT-IDE]]

Lo-tech XT-CF Board

2022-08-17T16:10:01Z

James: /* BIOS */

Lo-tech XT-CF Board

2022-08-17T16:09:17Z

James:

[[File:Peacon-xt-cf-assembled.JPG|right|300px|Lo-tech XT-CF Board Assembled (first prototype)]]
The [[lo-tech XT-CF Board]] is a bootable 8-bit ISA card with a CompactFlash header mounted so that the CF card is accessible through a [[#ISA Bracket|custom ISA expansion slot bracket]]. This card has been designed for use in IBM PC/XT, PC/AT and all compatible systems.

''Note: the current iteration of this card is the [[XT-CFv3]].''

Key Features:

*Replace dead MFM or RLL hard disks (and their controllers) with a cheap CompactFlash or microdrive media
*Easy to access CompactFlash card without opening the PC
*Reduce system power consumption (and hence load on the PSU) by as much as 30W
*Uses the [https://xtideuniversalbios.org/ XT-IDE Universal BIOS] (adapter type 'lo-tech XT-CF')
*Increase system performance - offers 5x the throughput of an [[ST-412]]
*32K in-system re-programmable ROM (24K free for any other ROM code)

The board is derived from the [[Dangerous Prototypes XT-IDE Boards | Dangerous Prototypes V2 board]], and uses the same Xilinx XC9572XL CPLD.

== Specifications ==

=== General ===

*8-bit ISA card with header for type-I or type-II CompactFlash media
*CompactFlash header configured to operate media in true-IDE mode
*500mA 3.3V regulator can drive microdrive or CompactFlash cards without any external power connection (330mA power budget for microdrives)
*Line driver for on-card and external activity LEDs (30mA power budget for external LED)
*Low-cost SMT Flash memory chip with 32K usable
*JTAG header for CPLD programming

=== Modes of Operation ===

*8-bit Port-mapped IO
*16-but Port-mapped IO (supported on most systems; provides a performance advantage with 8088 and 8086 CPUs)

Operating mode is configured in the BIOS and can be switched on-the-fly between modes using the [[lo-tech XT-CF Configuration Utility]]. The board is functionality identical to the [[XT-CF-lite]], and with one jumper-wire fitted can also implement ISA B8 line functionality of the XT-CFv2, allowing use in [[IBM Personal Computer XT System Board Slot 8]].

== PCB ==

[[File:Peacon-xt-cf.JPG|right|300px|Lo-tech XT-CF Board]]

=== Boardhouse Requirements ===

*8 mils clearances and minimum track width
*0.4mm minimum hole size
*Can be manufactured on a 100x100mm board
*Gold fingers are preferable but not required

=== Assembly Notes ===

*Thoroughly wash the PCB before assembly with Isopropynol
*Place the CF socket, CPLD and flash chip first
*Next place the VRM, LED driver and resistor networks
*Then place LEDs, resistors and SMT capacitors
*Next thoroughly wash the board using a toothbrush to ensure flux is removed from between SMT pins
*Next add the through-hole components (DIP switch, headers and 47uF capacitor), then wash again
*Before use inspect all connections with a magnifying glass to ensure there are no shorts between pins. Inspect the CF header leads as solder can sometimes flow up the leads during assembly causing a short away from the PCB itself.

=== Bill Of Materials ===

[http://www.farnell.com Farnell] Parts List:

{| class="wikitable" border="1"
|-
!Part(s)
!Description
!Package
!Value
!Qty Required
!Farnell Code
|-
| IC1 || XC9572 72-cell 3.3v CPLD || TQFP100 || - || 1 || 1193233
|-
| IC2 || SST39SF0x0A Flash || TSOP32 (8x14mm) || 1, 2 or 4Mb || 1 || 1829977
|-
| IC3 || SCHMITT TRIG, INV GATE 74LVC1G14 || SOT-25 || - || 1 || 1893833
|-
| VR1 || SPX3819M5-L-3-3 - LDO, 500MA, 3.3V, LOW NOISE || SOT-23-5 || - || 1 || 1831949
|-
| C1 || Low-ESR Electrolytic Capacitor || Radial, 5mm pitch, 10mm max diameter || 47uF to 100uF, 10V+ || 1 || 1692338 (future: SMD 1850100)
|-
| C2, C14 || Ceramic Capacitor (X5R or X7R) || 0805 || 10uF, 10V+ || 2 || 1833812
|-
| C12..13 || Ceramic Capacitor (X5R or X7R) || 0603 || 1uF, 10V+ || 2 || 1828801
|-
| C3..11 || Ceramic Capacitor (X5R or X7R) || 0603 || 0.1uF, 10V+ || 9 || 1414610
|-
| R1..2 || Resistor || 0603 || RESISTOR, 10K, 0.1W || 2 || 1469748
|-
| R3, R5 || Resistor || 0603 || RESISTOR, 1K, 0.1W || 2 || 2008355 or 1652848
|-
| R4 || Resistor || 0603 || RESISTOR, 270R, 0.1W || 1 || 2059585
|-
| R6 || Resistor || 0603 || RESISTOR, 5K6, 0.1W || 1 || 1739171
|-
| RN1, RN2 || Resistor Network || 1206 || RESISTOR NETWORK, 10K, ± 2% || 2 || 1770137
|-
| LED1 || Low-current LED || 0805 || LED, SMD || 1 || 1685055
|-
| DIP_SW || 9-way DIP switch || DIL || SWITCH, DIL, 9WAY || 1 || 1255227
|-
| CF1 || 3M N7E50-Q516 Compact Flash Header || - || 3M N7E50-Q516xx-x0 || 1 || 1267444
|-
| EXT.LED || 2-pin Header || - || HEADER, 1ROW, 2WAY || 1 || 3418285
|-
| JP1 || 3-pin Header || - || HEADER, 1ROW, 3WAY || 1 || 3418297
|-
| JTAG || 6-pin Header || - || HEADER, 2ROW, 6WAY || 1 || 3418492
|-
| - || Jumper for CF Card Voltage Selection || - || - || 1 || 1740370
|}

Notes:

*EXT.LED and R4 can be omited if external activity LED is not required
*LED and R5 can be omited if on-board activity LED is not required
*IC3, R4, R5, LED and EXT.LED can be omited if no activity LEDs are required

== ISA Bracket ==

[[file:peacon-xt-cf-bracket.png|200px|right|thumb|XT-CF Adapter ISA Bracket]]
*ISA Bracket Design per sketch
*To minimise production cost, design has no threaded holes (simple nut-and-bolt required)

== CPLD Logic ==

=== Downloads ===

*[{{SERVER}}/downloads/XT-CF/v1/XT-CFv1-r100-xsvf.zip CPLD XSVF File]
*[{{SERVER}}/downloads/XT-CF/v1/XT-CFv1-r100-ISE-Source.zip CPLD ISE Source Code]

=== Programming the CPLD ===

See [[lo-tech XT-CF CPLD Programming Guide]].

== ROM & BIOS ==

=== ROM ===

*Board design permits the use of [http://www.sst.com/dotAsset/40746.pdf SST39SF0x0A flash chips] (TSOP32, 8x14mm) of 1Mb, 2Mb or 4Mb capacity
*Regardless of the chip used, the first 32KB only will be mapped into the PC address space
*Base address configuration per [[#DIP Switch Settings|DIP Switch Settings]]

=== BIOS ===

*[{{SERVER}}/downloads/XT-CF/xtide-r566-xt-cf-master-slave.zip XT-CF Family BIOS] (configured for 300h)
*The BIOS should be configured using the (BIOS supplied) <tt>xtidecfg.com</tt> utility, then written out to the XT-CF adapter using the [[Lo-tech XT-CF flash utility]]
*For BIOS sources, see the [https://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS Google Code Home]

== Compatibility and Interoperability ==

=== Use with Other Cards ===

*The IO port address set via the DIP switches must match that set in the XTIDE Universal BIOS configuration utility
*The BIOS address can be changed via the DIP switches without changing the BIOS itself

=== Compatibility ===

*All CompactFlash media can be used. Media supporting multi-sector transfers will provide a performance advantage.
*The adapter can be used in any system supporting 8-bit ISA
*8-bit Port-mapped IO transfer mode is slowest but most compatible
*16-bit Port-mapped IO (BIU offload mode) is not supported on some early PC/XT clones, due to system logic errors
*ROM shadowing will offer significant performance gains on newer hardware, since the flash ROM is 8-bit so BIOS instructions can be fetched much more efficiently from system RAM

== DIP Switch Settings ==

{| class="wikitable" border="1"
!Switch
!Function
!On
!Off
|-
|1 || ROM Enable || Enabled || Disabled
|-
|2 || ROM Base Address || C800h || D000h
|-
|3 || IO Port Address || 300h || 320h
|-
|4** || ISA B8 Enable || Enabled || Disabled
|-
|5** || ISA B8 Function Type (if enabled) || PC-AT (Zero-wait-state) || PC-XT Slot 8
|-
|6* || Not used || - || -
|-
|7* || ISA B8 Output** || - || -
|-
|8* || Not used || - || -
|-
|9 || ROM Write Enable || Enabled || Disabled (ROM cannot be written)
|}

<nowiki>*</nowiki>Switches 6-8 must be OFF. Switch 9 can be left ON, since the flash chip includes Software Data Protection that prevents accidental corruption or overwriting.

<nowiki>**</nowiki>To use the ISA B8 function, wire a jumper from Sw7 resistor-side to ISA B8 pad (see [[:File:XT-CF-ISA-B8-Jumper-Wire.jpg|photo]]).

Default settings: ROM enabled, IO port 300h, ROM base C800h:

{| class="wikitable" border="1"
|-
!1 !!2 !!3 !!4 !!5 !!6 !!7 !!8 !!9
|-
| ON || ON || ON || OFF || OFF || OFF || OFF || OFF || ON
|}

Note that the IO base address is set within the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS] ROM image via the [http://code.google.com/p/xtideuniversalbios/wiki/Manual_v2_0_0#Using_XTIDECFG.COM_(XTIDE_Universal_BIOS_configuration_and_flash Universal BIOS Configuration and Flashing utility]. The IO address set within that utility must much that configured on the card. Should the IO port address be changed for any reason, the BIOS must be updated and re-flashed to the XT-CF card (using the [[lo-tech XT-CF flash utility]]).

The BIOS address is determined at boot time by the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS]. Since the code has been designed to be relocatable, the BIOS base address can be changed without the need to reconfigure the Universal BIOS.

== Known Issues ==

*Activity LED is lit when a CF card isn't inserted. Could be resolved by adding a 50k PU to /PDIAG.
*47uF through-hole capacitor holes are placed too wide (spaced for ~100V capacitors).
*Switch numbers are reversed in the schematic
*ISA B8 isn't connected, hence card cannot be used in slot 8 of IBM PC/XT (see note above)

== See Also ==

*[[lo-tech XT-CF Technical Reference]]
*[[Lo-tech XT-CF Boards]]

Lo-tech ISA CompactFlash Adapter FAQ

2022-08-17T10:42:29Z

James: /* What BIOS does the Card Use? */

== What Does It Do? ==

The [[Lo-tech ISA CompactFlash Adapter revision 2|Lo-tech ISA CompactFlash Adapter]] is a bootable storage adapter for IBM PC, PC/XT, PC/AT and compatible hardware - the board acts as a fixed disk controller, able to replace an aging MFM hard drive and controller. Thanks to the [http://code.google.com/p/xtideuniversalbios/ XTIDE Universal BIOS], the device can provide the maximum 8GB storage that is accessible by MS-DOS from a single solid-state storage media card (either CompactFlash or SD-Card).

== It's called 'ISA CompactFlash Adapter - Where's the CompactFlash Card Slot? ==

The [[Lo-tech ISA CompactFlash Adapter revision 2|Lo-tech ISA CompactFlash Adapter]] has been designed as a home-assembly electronics kit for the hobbyist and so uses only through-hole components for the basic functionality. The 40-pin IDE header enables the connection of low-cost and readily-available IDE to CompactFlash adapters, so avoiding the use of a fiddly surface-mount header and saving PCB space.

== Can SD Cards be used? ==

Yes, when used with an adapter based on the 'FC1306T (GP)' chip. See [{{SERVER}}/isa-compactflash-adapter-and-sd-cards/ blog entry] for more information.

== Are the Surface Mount Components Needed? ==

The design requires only through-hole components to work. Surface mount components on the solder side provide additional functionality:

*[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Device activity LED drive
*Selectable ROM address (rev.2b PCB)

Without these components, these functions cannot be used. The device activity signal provided by CompactFlash cards is typically too weak to power an LED directly, hence an otherwise unused gate in the optional SMT 'LS33 is used as an amplifier.

Some machines are known to be incompatible with the card select signal, including the Tandy 1000 series and the IBM PS/2 Model 30-286. In such machines:

*for rev.2 board, SMT components should '''not''' be populated
*for rev.2b board, components can be populated but JP3 should be left open

== Assembly ==

Start with the smallest components first; a suggested soldering order is:

#SMT components, if being fitted (note IC orientation; the bevelled edge is indicated on the silk-screen)
#Capacitors C1-C5
#C8 (note orientation; C8 positive leg is closest to C3)
#Resistor network (pin 1, marked with a dot, goes nearest IC1)
#IC sockets (note orientation; the notch is printed on the silkscreen)
#2-pin headers
#40-pin header
#Capacitor C6

The board should be cleaned before capacitor C6 is fitted.

== BIOS, Flashing and Reflashing ==

=== Is an EEPROM Programmer Needed? ===

No, the board ROM can be flashed in the host system from DOS using the [[Lo-tech XT-CF flash utility]].

=== What BIOS does the Card Use? ===

The card uses the [https://xtideuniversalbios.org/ XTIDE Universal BIOS], from R566.

*[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip Pre-configured XTIDE Universal BIOS R566 Binary File for Lo-tech ISA CompactFlash Adapter]
**This is the 'standard' 8KB BIOS image, and should be used in most installations.
**There is 24KB free, meaning additional option ROMs (for other devices) can also be hosted in the ISA CompactFlash Adapter
**To add other ROM images, append the required binaries using MS-DOS "COPY /B" command, then write the entire file using the [[Lo-tech XT-CF flash utility]]
*[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/offr566.zip Pre-configured BIOS based on R566 (FFh padded with BIOS at CC00h) Binary File for Lo-tech ISA CompactFlash Adapter]
**This is a 24KB ROM image, with the first 16KB padded with bytes of FFh.
**This image enables the use of the adapter in machines that are hard-wired to have 8- or 16KB at C800h provided by a ROM on the system board, and as such cannot have this ROM address provided by a device in an expansion slot.
**Machines needing this version include the Tandy 1000 RL/HD

If building from source, run XTIDECFG.COM to configure the IDE_XT.BIN file, select controller XT-CF and 300h, then save the file. Then exit to DOS and use FLASH to write it to the card (see below).

=== How is the BIOS Programmed? ===

The BIOS cannot be programmed with the XT-IDE Universal BIOS XTIDECFG utility; instead the [[Lo-tech XT-CF flash utility]] should be used once the BIOS image file has been configured and saved (to disk) using XTIDECFG.

*[{{SERVER}}/downloads/XT-IDE/lo-tech-Flash-utility.zip Lo-tech FLASH utility binary]

=== Can the Board be Re-Programmed, i.e. BIOS Upgraded? ===

Yes, the specified flash ROM chips can be re-programmed around 1,000 times.

== First BIOS Flash Attempt Fails ==

*Check the jumper on JP1 is fitted.
*Check the soldering and orientation of IC2 and IC3

== BIOS Re-flashing Fails ==

In some systems, the first flash is performed successfully but further flashing fails. This is typically caused by BIOS ROM shadowing, which later machines used to run ROM code from fast RAM instead of slower ROM chips. This can be resolved by either disabling ROM shadowing in the BIOS, if the option is provided, or by JP1:

*Remove JP1, then power on the machine
*Once completely booted, install JP1 (with the machine running). The jumper connects the ROM-CS signal generated by one of the '688's; the signal is isolated from the host system and therefore this cannot damage the host.
*Next run the flash utility, and the flash should be successfully programmed.

== Initialisation Problems ==

For example:

*Machine hangs during POST or won't POST with ISA CompactFlash Adapter Installed
*BIOS cannot be flashed onto card, or flashing causes system lockup or hang
*BIOS flashing was successful, but the XTIDE Universal BIOS never appears in the POST

For these issues:

*Check the soldering, especially for shorts around U1
*Some machines, such as the IBM PS/2 Model 30-286, are not compatible with the CARDSEL/ZWS signal generated by U1
**Remove U1 (for example using a hot-air rework tool).
*If the XTIDE Universal BIOS never appears during the POST:
**Rev.2b: if R4 is not fitted, ensure JP2 is closed (setting the ROM to C800h)
**Rev.2b: try alternate ROM address D800h
**try alternate BIOS images:
***[{{SERVER}}/downloads/XT-CF/ISA-CF-BIOS-r567-late-init.zip very late initialisation option]
***[{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/offr566.zip FFh padded image (BIOS at CC00h)]
**ensure that the system ROM is scanning for option ROMs (original IBM PC 5150 and original Tandy 1000 ROM do not scan for option ROMs, for example)
**ensure selected ROM address is available
**If another option ROM at the selected ROM address (C800h, D800h) cannot be disabled, dump that BIOS to a file (usually 4, 8 or 16KB), then append the standard BIOS image (<tt>COPY /B</tt>), then flash the new, larger file to the adapter (another machine might be needed to perform the flash operation). This will result in the on-board BIOS and flash chip on the adapter responding with the same data, and the XTIDE Universal BIOS being detected at a higher memory address (like CA00h or CC00h).

== CompactFlash Cards are Not Detected ==

*Check the soldering and orientation of IC1, IC4, IC5 and RN1
*Check the CompactFlash card has adequate power supply. Is using an adapter connected to the board via a ribbon cable, a separate 5V supply must be provided (usually via a 3.5" floppy disk style power connector)
*Check the CompactFlash card adapter is set to 5V operation
*If using a dual CompactFlash adapter, try a single CompactFlash card configured as Master

== CompactFlash Cards configured as Slave are Not Detected ==

Not all CompactFlash cards support a slave configuration. Try a different card.

== SD Cards are Not Detected ==

If using an SD Card adapter, check it is built on the 'FC1306T (GP)' chip. See [{{SERVER}}/isa-compactflash-adapter-and-sd-cards/ blog entry] for more information.

== Hard Disk Device is Not Detected ==

Only hard disks supporting ATA-2 command set can be used.

== The Machine Hangs at 'Booting C' ==

This occurs because the boot sector written by the CompactFlash card manufacturer is not compatible with 8088 CPU in most cases. This can be resolved in one of two ways:

=== Method 1 ===

Wipe the boot sector using the [[WipeDisk|Lo-tech WIPEDISK utility]] and then start over - boot from a floppy (press A when the XTIDE Universal BIOS message appears) then run FDISK to create a primary and active partition, then reboot again from a floppy and run <tt>FORMAT /S</tt> to copy on the DOS files. ''Note that this method will completely erase all data on the device.''

=== Method 2 ===

If using MS-DOS 6.22, boot from a floppy (press A when the XTIDE Universal BIOS message appears) then run FDISK /MBR. This will re-write the executable boot-sector code, leaving the partition table and partition data intact.

== See Also ==

*[[Lo-tech ISA CompactFlash Adapter revision 2|Lo-tech ISA CompactFlash Adapter]]

XTIDE Universal BIOS

2022-07-16T09:55:10Z

James: /* Programming Lo-tech Storage Boards */

'''XTIDE Universal BIOS makes it possible to use ATA hard disks or Compact Flash cards on old PC's. The XTIDE Universal BIOS can be used on any IBM PC, XT, AT or 100% compatible system.'''

== Official Project Site ==

*'''[https://xtideuniversalbios.org xtideuniversalbios.org]'''

The official project site is hosted by Lo-tech.

== License of Use ==

The XTIDE Universal BIOS project is run under [http://www.gnu.org/licenses/gpl-2.0.html GNU General Public License version 2].

In addition to that license through which the source code is made available, binary downloads provided from Lo-tech.co.uk are subject to the [[Terms and Conditions|Lo-tech Terms and Conditions of Use]].

== Building from Source ==

For those wishing to build from source, for example for specific functionality not provided by the standard builds, instructions are maintained on the project site '''[https://xtideuniversalbios.org/wiki/BuildInstructions here]'''.

== Binary Downloads ==

Each release is automatically compiled, and the binaries are available at [https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries].

The binary images must be configured to the requirements of the machine using XTIDECFG.COM, saved, and finally written out to the EEPROM or EPROM.

== Configuring the BIOS ==

The provided binaries must be configured before use. This is done with the XTIDECFG.COM utility, which is included in the download. This is an MSDOS utility. The steps to get the BIOS onto the machine are:

#Download the latest build from [https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries]:
#*XTIDECFG.COM, and
#*The appropriate XT_xxx.bin file (see table below)
#Copy the two files to an MSDOS bootable floppy disk
#Boot the machine from the floppy
#Configure the BIOS binary by running XTIDECFG.COM
#*Open the XT_xxx.bin file
#*Configure according to system requirements
#*Save the file
#*For EPROMs or read-only cards (such as network cards), write out the configured file using an EPROM programmer off-system
#*For 2816/2864 series EEPROMs in supported cards such as the original XTIDE, write the configured file directly to the EPROM using the XTIDECFG.COM utility
#*For 29010/29020 EEPROMs as used by most Lo-tech boards, write the configured file using the [[Lo-tech XT-CF flash utility]] (see below)
#Reboot the machine and run FDISK and FORMAT as required

== Programming Lo-tech Storage Boards ==

Lo-tech storage boards use SST 29xxx series EEPROMs, which cannot be written to by the XTIDECFG.COM utility. However, the BIOS file (XT_xxx.bin) still needs to be configured and saved using XTIDECFG.COM, before the file can be written to the Lo-tech boards using the [[Lo-tech XT-CF flash utility]].

For users of Lo-tech CompactFlash based boards, [{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip a pre-configured XTIDE Universal BIOS (built on r566]) is provided, which can be written directly to the cards using the [[Lo-tech XT-CF flash utility]] without the additional configuration step. See [{{SERVER}}/wiki/Lo-tech_ISA_CompactFlash_Adapter_FAQ#What_BIOS_does_the_Card_Use.3F here] for more information.

For users of the [[Lo-tech 8-bit IDE Adapter]], a special build based on r567 is available - see [{{SERVER}}/wiki/Lo-tech_8-bit_IDE_Adapter#ROM_BIOS_.26_BIOS_Flashing here].

== XTIDE BIOS Files ==

[https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries The pre-built binaries download centre] provides a number of builds for specific use-cases as detailed below.

{|class="wikitable"
!File Name !! Use-Case !! Notes
|-
|ide_386.bin || Any PC with an 80386 or higher CPU || Standard build (8KB)
|-
|ide_386l.bin || Any PC with an 80386 or higher CPU || Large build (10KB)
|-
|ide_286.bin || Any PC with an 80286 or higher CPU || Standard build (8KB)
|-
|ide_286l.bin || Any PC with an 80286 or higher CPU || Large build (10KB)
|-
|ide_tiny.bin || Any PC || Tiny build (4KB)
|-
|ide_xt.bin || Any PC/XT class machine with 8088 or 8086 CPU (or above) || Standard build (8KB)
|-
|ide_xtl.bin || Any PC/XT class machine with 8088 or 8086 CPU (or above) || Large build (10KB)
|-
|ide_xtp.bin || Any PC/XT class machine with NEC V20/V30 CPU (or equivalent providing 80186 instruction set) || Standard build (8KB)
|-
|ide_xtpl.bin || Any PC/XT class machine with NEC V20/V30 CPU (or equivalent providing 80186 instruction set) || Large build (10KB)
|}

The XTIDECFG.COM utility is used to configure any of the above binary files, prior to writing to the EEPROM. EEPROMs can be written in-system to Lo-tech boards using the [[Lo-tech XT-CF flash utility]].

The standard builds include a 'hot-key' user interface where users can boot from floppy by pressing 'A' at the initialisation screen and support for serial-connected drives. Large builds also include a full boot menu. The Tiny build includes only the most basic functionality, to enable the use of the BIOS on 4KB ROMs (serial devices are not supported).

== Performance ==

A number of factors impact the performance of devices operating via the XTIDE Universal BIOS.

*Choose the BIOS binary file that most closely matches your system.
**If you have a V20 or V30 CPU, use the ide_xpl.bin file. This makes use of loop instructions not available on 8088/8086 and will provide a big performance increase on these systems.
**Even if you have an 'XT Class' 80286 based system, such as the Tandy 1000TL, use the ide_286.bin file.
*On slower machines, the multi-sector transfer capabilities of the storage device itself can greatly impact performance. Some devices, in particular many CompactFlash cards, allow the system to transfer only one sector at a time (512 bytes), which means the BIOS code must loop through sector read request code every 512 bytes. This is much slower than transferring a larger block of data in one go, as would be possible with a device supporting multi-sector transfers.
*Many 8-bit ISA 'XTIDE' derivatives support '16-bit transfers' using port mapping techniques that offload the effort of breaking 16-bit transfers into two 8-bit transfers to the system bus interface unit. This is known as 'Bus Interface Offload Mode' in the XTIDE Universal BIOS (BIU mode) and offers significant performance advantages for 8-bit ISA cards such as the original XTIDE card and most Lo-tech boards.
*When using the XTIDE Universal BIOS on later machines (386/486/Pentium), be sure to enable ROM shadowing in the BIOS for the region where the ROM is stored. For example, if the ROM is at C800h, enable ROM shadowing for C800h to CA00h (assuming standard 8KB build). This will greatly improve performance, since otherwise each instruction in the ROM code must be fetched over the slow 8-bit ISA bus, instead of from system memory or CPU cache. Note that ROM Shadowing will likely need to be disabled in order to (re)program the card.

== See Also ==

*Former project hosting: https://code.google.com/p/xtideuniversalbios/
*[http://www.vintage-computer.com/vcforum/showthread.php?29749-XTIDE-Universal-BIOS-v2-0-0-beta-testing-thread VintageComputer.com BIOS v2.0 Development Thread]

XTIDE Universal BIOS

2022-07-16T09:35:48Z

James: /* Performance */

'''XTIDE Universal BIOS makes it possible to use ATA hard disks or Compact Flash cards on old PC's. The XTIDE Universal BIOS can be used on any IBM PC, XT, AT or 100% compatible system.'''

== Official Project Site ==

*'''[https://xtideuniversalbios.org xtideuniversalbios.org]'''

The official project site is hosted by Lo-tech.

== License of Use ==

The XTIDE Universal BIOS project is run under [http://www.gnu.org/licenses/gpl-2.0.html GNU General Public License version 2].

In addition to that license through which the source code is made available, binary downloads provided from Lo-tech.co.uk are subject to the [[Terms and Conditions|Lo-tech Terms and Conditions of Use]].

== Building from Source ==

For those wishing to build from source, for example for specific functionality not provided by the standard builds, instructions are maintained on the project site '''[https://xtideuniversalbios.org/wiki/BuildInstructions here]'''.

== Binary Downloads ==

Each release is automatically compiled, and the binaries are available at [https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries].

The binary images must be configured to the requirements of the machine using XTIDECFG.COM, saved, and finally written out to the EEPROM or EPROM.

== Configuring the BIOS ==

The provided binaries must be configured before use. This is done with the XTIDECFG.COM utility, which is included in the download. This is an MSDOS utility. The steps to get the BIOS onto the machine are:

#Download the latest build from [https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries]:
#*XTIDECFG.COM, and
#*The appropriate XT_xxx.bin file (see table below)
#Copy the two files to an MSDOS bootable floppy disk
#Boot the machine from the floppy
#Configure the BIOS binary by running XTIDECFG.COM
#*Open the XT_xxx.bin file
#*Configure according to system requirements
#*Save the file
#*For EPROMs or read-only cards (such as network cards), write out the configured file using an EPROM programmer off-system
#*For 2816/2864 series EEPROMs in supported cards such as the original XTIDE, write the configured file directly to the EPROM using the XTIDECFG.COM utility
#*For 29010/29020 EEPROMs as used by most Lo-tech boards, write the configured file using the [[Lo-tech XT-CF flash utility]] (see below)
#Reboot the machine and run FDISK and FORMAT as required

== Programming Lo-tech Storage Boards ==

Lo-tech storage boards use SST 29xxx series EEPROMs, which cannot be written to by the XTIDECFG.COM utility. However, the BIOS file (XT_xxx.bin) still needs to be configured and saved using XTIDECFG.COM, before the file can be written to the Lo-tech boards using the [[Lo-tech XT-CF flash utility]].

For users of Lo-tech CompactFlash based boards, [{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip a pre-configured XTIDE Universal BIOS (built on r566] is provided, which can be written directly to the cards using the [[Lo-tech XT-CF flash utility]] without the additional configuration step. See [{{SERVER}}/wiki/Lo-tech_ISA_CompactFlash_Adapter_FAQ#What_BIOS_does_the_Card_Use.3F here] for more information.

For users of the [[Lo-tech 8-bit IDE Adapter]], a special build based on r567 is available - see [{{SERVER}}/wiki/Lo-tech_8-bit_IDE_Adapter#ROM_BIOS_.26_BIOS_Flashing here].

== XTIDE BIOS Files ==

[https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries The pre-built binaries download centre] provides a number of builds for specific use-cases as detailed below.

{|class="wikitable"
!File Name !! Use-Case !! Notes
|-
|ide_386.bin || Any PC with an 80386 or higher CPU || Standard build (8KB)
|-
|ide_386l.bin || Any PC with an 80386 or higher CPU || Large build (10KB)
|-
|ide_286.bin || Any PC with an 80286 or higher CPU || Standard build (8KB)
|-
|ide_286l.bin || Any PC with an 80286 or higher CPU || Large build (10KB)
|-
|ide_tiny.bin || Any PC || Tiny build (4KB)
|-
|ide_xt.bin || Any PC/XT class machine with 8088 or 8086 CPU (or above) || Standard build (8KB)
|-
|ide_xtl.bin || Any PC/XT class machine with 8088 or 8086 CPU (or above) || Large build (10KB)
|-
|ide_xtp.bin || Any PC/XT class machine with NEC V20/V30 CPU (or equivalent providing 80186 instruction set) || Standard build (8KB)
|-
|ide_xtpl.bin || Any PC/XT class machine with NEC V20/V30 CPU (or equivalent providing 80186 instruction set) || Large build (10KB)
|}

The XTIDECFG.COM utility is used to configure any of the above binary files, prior to writing to the EEPROM. EEPROMs can be written in-system to Lo-tech boards using the [[Lo-tech XT-CF flash utility]].

The standard builds include a 'hot-key' user interface where users can boot from floppy by pressing 'A' at the initialisation screen and support for serial-connected drives. Large builds also include a full boot menu. The Tiny build includes only the most basic functionality, to enable the use of the BIOS on 4KB ROMs (serial devices are not supported).

== Performance ==

A number of factors impact the performance of devices operating via the XTIDE Universal BIOS.

*Choose the BIOS binary file that most closely matches your system.
**If you have a V20 or V30 CPU, use the ide_xpl.bin file. This makes use of loop instructions not available on 8088/8086 and will provide a big performance increase on these systems.
**Even if you have an 'XT Class' 80286 based system, such as the Tandy 1000TL, use the ide_286.bin file.
*On slower machines, the multi-sector transfer capabilities of the storage device itself can greatly impact performance. Some devices, in particular many CompactFlash cards, allow the system to transfer only one sector at a time (512 bytes), which means the BIOS code must loop through sector read request code every 512 bytes. This is much slower than transferring a larger block of data in one go, as would be possible with a device supporting multi-sector transfers.
*Many 8-bit ISA 'XTIDE' derivatives support '16-bit transfers' using port mapping techniques that offload the effort of breaking 16-bit transfers into two 8-bit transfers to the system bus interface unit. This is known as 'Bus Interface Offload Mode' in the XTIDE Universal BIOS (BIU mode) and offers significant performance advantages for 8-bit ISA cards such as the original XTIDE card and most Lo-tech boards.
*When using the XTIDE Universal BIOS on later machines (386/486/Pentium), be sure to enable ROM shadowing in the BIOS for the region where the ROM is stored. For example, if the ROM is at C800h, enable ROM shadowing for C800h to CA00h (assuming standard 8KB build). This will greatly improve performance, since otherwise each instruction in the ROM code must be fetched over the slow 8-bit ISA bus, instead of from system memory or CPU cache. Note that ROM Shadowing will likely need to be disabled in order to (re)program the card.

== See Also ==

*Former project hosting: https://code.google.com/p/xtideuniversalbios/
*[http://www.vintage-computer.com/vcforum/showthread.php?29749-XTIDE-Universal-BIOS-v2-0-0-beta-testing-thread VintageComputer.com BIOS v2.0 Development Thread]

XTIDE Universal BIOS

2022-07-16T09:30:51Z

James: Expanded to include deployment steps and table listing the pre-built binaries.

'''XTIDE Universal BIOS makes it possible to use ATA hard disks or Compact Flash cards on old PC's. The XTIDE Universal BIOS can be used on any IBM PC, XT, AT or 100% compatible system.'''

== Official Project Site ==

*'''[https://xtideuniversalbios.org xtideuniversalbios.org]'''

The official project site is hosted by Lo-tech.

== License of Use ==

The XTIDE Universal BIOS project is run under [http://www.gnu.org/licenses/gpl-2.0.html GNU General Public License version 2].

In addition to that license through which the source code is made available, binary downloads provided from Lo-tech.co.uk are subject to the [[Terms and Conditions|Lo-tech Terms and Conditions of Use]].

== Building from Source ==

For those wishing to build from source, for example for specific functionality not provided by the standard builds, instructions are maintained on the project site '''[https://xtideuniversalbios.org/wiki/BuildInstructions here]'''.

== Binary Downloads ==

Each release is automatically compiled, and the binaries are available at [https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries].

The binary images must be configured to the requirements of the machine using XTIDECFG.COM, saved, and finally written out to the EEPROM or EPROM.

== Configuring the BIOS ==

The provided binaries must be configured before use. This is done with the XTIDECFG.COM utility, which is included in the download. This is an MSDOS utility. The steps to get the BIOS onto the machine are:

#Download the latest build from [https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries]:
#*XTIDECFG.COM, and
#*The appropriate XT_xxx.bin file (see table below)
#Copy the two files to an MSDOS bootable floppy disk
#Boot the machine from the floppy
#Configure the BIOS binary by running XTIDECFG.COM
#*Open the XT_xxx.bin file
#*Configure according to system requirements
#*Save the file
#*For EPROMs or read-only cards (such as network cards), write out the configured file using an EPROM programmer off-system
#*For 2816/2864 series EEPROMs in supported cards such as the original XTIDE, write the configured file directly to the EPROM using the XTIDECFG.COM utility
#*For 29010/29020 EEPROMs as used by most Lo-tech boards, write the configured file using the [[Lo-tech XT-CF flash utility]] (see below)
#Reboot the machine and run FDISK and FORMAT as required

== Programming Lo-tech Storage Boards ==

Lo-tech storage boards use SST 29xxx series EEPROMs, which cannot be written to by the XTIDECFG.COM utility. However, the BIOS file (XT_xxx.bin) still needs to be configured and saved using XTIDECFG.COM, before the file can be written to the Lo-tech boards using the [[Lo-tech XT-CF flash utility]].

For users of Lo-tech CompactFlash based boards, [{{SERVER}}/downloads/XT-IDE/lo-tech-isa-compactflash-adapter/xtide-r566-xt-cf-master-slave.zip a pre-configured XTIDE Universal BIOS (built on r566] is provided, which can be written directly to the cards using the [[Lo-tech XT-CF flash utility]] without the additional configuration step. See [{{SERVER}}/wiki/Lo-tech_ISA_CompactFlash_Adapter_FAQ#What_BIOS_does_the_Card_Use.3F here] for more information.

For users of the [[Lo-tech 8-bit IDE Adapter]], a special build based on r567 is available - see [{{SERVER}}/wiki/Lo-tech_8-bit_IDE_Adapter#ROM_BIOS_.26_BIOS_Flashing here].

== XTIDE BIOS Files ==

[https://xtideuniversalbios.org/binaries xtideuniversalbios.org/binaries The pre-built binaries download centre] provides a number of builds for specific use-cases as detailed below.

{|class="wikitable"
!File Name !! Use-Case !! Notes
|-
|ide_386.bin || Any PC with an 80386 or higher CPU || Standard build (8KB)
|-
|ide_386l.bin || Any PC with an 80386 or higher CPU || Large build (10KB)
|-
|ide_286.bin || Any PC with an 80286 or higher CPU || Standard build (8KB)
|-
|ide_286l.bin || Any PC with an 80286 or higher CPU || Large build (10KB)
|-
|ide_tiny.bin || Any PC || Tiny build (4KB)
|-
|ide_xt.bin || Any PC/XT class machine with 8088 or 8086 CPU (or above) || Standard build (8KB)
|-
|ide_xtl.bin || Any PC/XT class machine with 8088 or 8086 CPU (or above) || Large build (10KB)
|-
|ide_xtp.bin || Any PC/XT class machine with NEC V20/V30 CPU (or equivalent providing 80186 instruction set) || Standard build (8KB)
|-
|ide_xtpl.bin || Any PC/XT class machine with NEC V20/V30 CPU (or equivalent providing 80186 instruction set) || Large build (10KB)
|}

The XTIDECFG.COM utility is used to configure any of the above binary files, prior to writing to the EEPROM. EEPROMs can be written in-system to Lo-tech boards using the [[Lo-tech XT-CF flash utility]].

The standard builds include a 'hot-key' user interface where users can boot from floppy by pressing 'A' at the initialisation screen and support for serial-connected drives. Large builds also include a full boot menu. The Tiny build includes only the most basic functionality, to enable the use of the BIOS on 4KB ROMs (serial devices are not supported).

== Performance ==

A number of factors impact the performance of devices operating via the XTIDE Universal BIOS.

*Choose the BIOS binary file that most closely matches your system.
**If you have a V20 or V30 CPU, use the ide_xpl.bin file. This makes use of loop instructions not available on 8088/8086 and will provide a big performance increase on these systems.
**Even if you have an 'XT Class' 80286 based system, such as the Tandy 1000TL, use the ide_286.bin file.
*On slower machines, the multi-sector transfer capabilities of the storage device itself can greatly impact performance. Some devices, in particular many CompactFlash cards, allow the system to transfer only one sector at a time (512 bytes), which means the BIOS code must loop through sector read request code every 512 bytes. This is much slower than transferring a larger block of data in one go, as would be possible with a device supporting multi-sector transfers.
*Many 8-bit ISA 'XTIDE' derivatives support '16-bit transfers' using port mapping techniques that offload the effort of breaking 16-bit transfers into two 8-bit transfers to the system bus interface unit. This is known as 'Bus Interface Offload Mode' in the XTIDE Universal BIOS (BIU mode) and offers significant performance advantages for 8-bit ISA cards such as the original XTIDE card and most Lo-tech boards.
*When using the XTIDE Universal BIOS on later machines (386/486/Pentium), be sure to enable ROM shadowing in the BIOS for the region where the ROM is stored. For example, if the ROM is at C800h, enable ROM shadowing for C800h to CA00h (assuming standard 8KB build). This will greatly improve performance, since otherwise each instruction in the ROM code must be fetched over the slow 8-bit ISA bus, instead of from system memory or CPU cache.

== See Also ==

*Former project hosting: https://code.google.com/p/xtideuniversalbios/
*[http://www.vintage-computer.com/vcforum/showthread.php?29749-XTIDE-Universal-BIOS-v2-0-0-beta-testing-thread VintageComputer.com BIOS v2.0 Development Thread]

Lo-tech ISA USB Adapter

2022-07-16T07:19:18Z

James:

[[File:Lo-tech-ISA-USB-Adapter-PCB-Front.JPG|right|300px|Lo-tech ISA USB Adapter PCB]]

The [[Lo-tech ISA USB Adapter]] is a bootable storage adapter for IBM PC, PC/XT, PC/AT and compatible hardware - essentially any PC with an ISA slot, enabling a standard USB flash drive to be used. This eliminates the dependence on ageing hard disks and floppy disks, and makes data exchange with a modern PC easy. The design is based on the CH375 USB chip and is a development of the [[Lo-tech ISA CompactFlash Adapter revision 2b]].

The BIOS ROM used by the card (available [https://gitlab.com/hakfoo1/v40-bios/-/tree/CH375-Workarounds/ here]) enable the host PC to boot from storage presented by the adapter, which appears in DOS as an ordinary fixed disk (i.e., drive C, D, etc). No DOS drivers are needed. Note that the maximum partition size under MS-DOS is 2GB, meaning a total of 8GB can be accessed and the current BIOS provides up to 504MB. For users not requiring ROM boot, a CONFIG.SYS driver will also be available soon.

The PCB itself is a 4-layer, small form factor 8-bit ISA adapter. Building this PCB requires some surface-mount (SMT) components, the smallest being 0603 capacitors. Mounting holes are provided for a custom ISA slot bracket, which can be 3D printed in plastic at home, or from commercial vendors in various metals.

The design provides:

*Bootable storage adapter for 8-bit PCs
*Small form-factor, to enable use in machines with limited expansion slot space such as the Tandy 1000HX, Sinclair PC200 and Amstrad PC-20
*[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Selectable BIOS address - C800h or D800h

The BIOS is provided through an in-system re-programmable 32KB flash-based ROM, and since the BIOS is only 8KB, 24KB is available for other purposes, and is byte-programmable - the board can therefore function as a universal ROM board.

The board uses the CH375 USB interface and provides optimised transfer speed for PC/XT class machines by using shifted port mapping, so enabling 16-bit instructions. This improves the performance to about 170KB/s at 4.77MHz.

== Specifications ==

=== General ===

*8-bit ISA card with standard USB socket for connection of USB flash drive
*Line driver for external activity LEDs (12mA power budget)
*[[IBM Personal Computer XT System Board Slot 8]] compatibility
*Low-cost flash memory chip for boot ROM, with 32KB usable
*Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
*Resource requirements:
**IO ports 2C0-2C8h
**ROM: 32KB at C800h or D800h

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:Lo-tech-ISA-USB-adapter-schematic.png
File:Lo-tech-ISA-USB-Adapter-PCB-Front.JPG
File:Lo-tech-ISA-USB-Adapter-PCB-Back.JPG
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''.

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Package !! Qty !! Farnell !! Mouser
|-
|IC1, IC3 || 74HCT688N || DIP-20 || 2 || 382504 || 771-74HCT688N
|-
|IC2 || SST39SF010A-70-4C-PHE || DIP-32 || 1 || 1896595 || 804-39SF010A7CPHE
|-
|IC4 || CH375 || SOIC-28 || 1 || - || -
|-
|IC5 || 74HCT245N || DIP-20 || 1 || 9591931 || 595-SN74HCT245N
|-
|C1-3, C5 || 0.1uF Ceramic Capacitor || C025-030X050 || 4 || 2112751 || 581-SR205E104MAR or 581-SR205C104KAR
|-
|C6 || 10uF Electrolytic Capacitor || E2-5 || 1 || 8767084 || 647-UVR1C100MDD
|-
|C7 || CAPACITOR, 0.1UF, 50V || 0805 || 2 || 1612208 || VJ0805V104MXBPW1BC
|-
|C9 || 0.01uF Ceramic || 0603 || 1 || - || 963-UMK107B7103KAHT
|-
|C10 || 0.1uF Ceramic || 0603 || 2 || - || 963-UMK107BJ104KAHT
|-
|C12-13 || 15-30pF Ceramic || 0603 || 2 || || 581-06035C220JAT2A
|-
|C14, C15 || 100uF Electrolytic Capacitor || E2-5 || 1 || - || 647-UVR1A101MDD
|-
|IC Socket (DIP32) || - || DIL32 || 1 || 1654375 || 571-1-2199300-2 517-4832-6000-CP
|-
|IC Socket (DIP20) || - || DIL20 || 3 || 1101349 || 571-1-2199298-6 649-DILB20P-223TLF
|-
|JP1, JP2, JP3, LED || - || 1x2 Pin Header || 4 || 1593411 || 855-M20-9990246 653-XG8S-0231
|-
|JP4 || - || 2x2 Pin Header || 1 || - || 517-9612046804AR
|-
| - || - || 2-pin jumper || 4 || 2396301 || 806-SX1100-A
|-
|U1 || SN74LS33D || SOIC-14 || 1 || 1752958 || 595-SN74LS33D
|-
|R1, R2, R4 || RESISTOR, 10K, 125MW || 0805 || 3 || 1612522 || 71-CRCW0805J-10K-E3
|-
|R3 || RESISTOR, 0.125W 1% 270R || 0805 || 1 || 1652970 || 71-CRCW0805270RJNEA
|-
|R5 || RESISTOR, 0.125W 1% 2R || 0805 || 1 || 1652970 || 71-CRCW08052R00FKEA
|-
|R6 || RESISTOR, 10K, 125MW || 0204/7 || 1 || 9342419 || 270-10K-RC
|-
|X1 || HC49 Crystal, 12MHz ±0.4‰ || - || 1 || - || 774-ATS12A-E
|-
|HD1 || USB Connectors RA USB A || - || 1 || - || 523-UE27AC5410H
|}

*Board design permits the use of a range of DIP-32 flash chips (1, 2 or 4Mb):
**[{{SERVER}}/downloads/manuals/SST/SST39SF0x0.pdf SST39SF0x0A] (SST39SF010A, SST39SF020A, SST39SF040A)
**[{{SERVER}}/downloads/manuals/AMIC/AMIC-A29010.pdf AMIC A29010]
**AMIC chips appear to have been discontinued (as as Nov-13)
*Regardless of the chip used, 32KB is presented at C800h (JP2 closed) or D800h (JP2 open and R4 fitted)

Note that when assembling SMT components, additional flux will also be needed (such as Edsyn FL22, Farnell order code 3059091).

== Configuration ==

*JP1: ROM enable (closed = enabled)
*JP2: ROM Address Selection - closed = C800h, open (and R4 fitted) = D800h
*JP3: Slot-8/ZWS Function (closed = enabled) - requires SMT components
*JP4: Port mode
**Std - 8-bit transfers, registers mapped at 2C0h, 2C1h
**Fast - 16-bit transfers, registers mapped at 2C0h, 2C2h (not supported by alpha BIOS)

An external LED can be attached to the 2-pin LED header only if the optional components (on the rear of the PCB) are populated. Current limit for LED is 12mA.

The IO port address (2C0h - 2C8h) is fixed.

== Build & Test ==

For additional help, please [{{SERVER}}/get-in-touch/ send an email].

=== Construction ===

*Find a suitable work surface with plenty of light. A car-cleaning sponge is useful to rest the PCB on since components are held nicely in place under the PCB by the soft surface, which can also be easily turned around as a whole with components not yet soldered
*Start with the SMT components, then proceed with the least tall components, so that they are held full in place with the solder side up
*When soldering IC sockets or ICs, ensure the notches are at the correct end as indicated by the PCB silkscreen
*Note the correct orientation of the polarised capacitors C6, C14 and C15.
*Wash all flux residues off once complete using isopropynol (for example with a toothbrush)
*Check closely with a magnifying glass all joints. Check especially for bridges between SMT pins

=== BIOS Flashing (Programming) ===

''The following assumes JP2 is closed, providing the ROM at C800h''

The flash chip is programmed with the [[Lo-tech XT-CF flash utility]]. To program the board, make a DOS boot disk (utilities have been tested on MS-DOS 2.11, 3.3 and 6.22) and add the BIOS binary file and the flash utility. Install the Lo-tech ISA CompactFlash Adapter in the machine and boot from the floppy, then flash the ROM thus:

A:\>flash v40-bios.bin c800

== Errata ==

The silkscreen incorrectly documents the fixed IO port range as 260-26Fh; the CH375 is at 2C0h.

== Downloads ==

*[https://gitlab.com/hakfoo1/v40-bios/-/tree/CH375-Workarounds/ Beta BIOS]
*[{{SERVER}}/downloads/isa-usb/CH375-datasheet.pdf CH375 datasheet]

Config.sys driver (for non-bootable use) coming soon.

== See Also ==

*[[Lo-tech ISA USB Adapter FAQ]]
*[[lo-tech XT-CF Boards]]

Lo-tech RPi VGA Adapter

2022-07-12T19:46:15Z

James:

[[File:Lo-tech-VGA-interface-board-mounted.jpg|right|300px]]
The [[Lo-tech RPi VGA Adapter]] is a high-quality display board that provides second-screen capabilities to Raspberry Pi boards equipped with 40-pin GPIO header. The two screens can be connected concurrently and used independently, and are both powered directly by the RPi’s GPU and so achieve the same graphics performance.

Key Features:

*VGA Interface for RaspberryPi SBCs with 40-pin GPIO header (Model A+/B+/2/3/4)
*Standard VGA DSUB connector, supports all video modes up to 1080p
*Resistor ladder type DAC, with 8-bit resolution on each channel (888 format)
*Buffered H-Sync and V-Sync ensures all GPIOs operate within their design current rating
*ESD protection to IEC−61000−4−2 Level 4
*FCC Class A Compliant and EU Council Directive 2004/108/EC Class B Compliant
*Natively supported in Raspbian Jessie via dpi24.dtb overlay
*Can be used as primary display or as a second (independent) display in addition to the on-board HDMI output

The board has been designed to fit directly on top of the RaspberryPi following the HAT physical dimensions (this board does not however provide the I2C EEPROM function required for HAT auto-configuration).

'''This product is available online [https://texelec.com/product/lo-tech-rpi-vga-board/ via the TexElec store].'''

<gallery widths="150px" heights="125px" perrow="3">
File:Lo-tech-VGA-interface-board-front.jpg
File:Lo-tech-VGA-interface-board-front-assembled.JPG
File:Lo-tech-VGA-interface-board-mounted.jpg
</gallery>

=== Raspbian Configuration ===

Raspbian Jessie provides native support for the parallel display interface provided via the GPIO header with alternate mode 2 via an overlay. This can be enabled via <tt>config.txt</tt> on the boot partition,

<source lang=bash>
dtoverlay=dpi24
enable_dpi_lcd=1
display_default_lcd=1
dpi_group=2
dpi_mode=16
dpi_output_format=0x17
</source>

Monitor resolution is determined by <tt>dpi_mode</tt> parameter:

{|class="wikitable"
!dpi_mode value !!Resolution !!Frequency
|-
| 4 || 640x480 || 60Hz
|-
| 9 || 800x600 || 60Hz
|-
| 16 || 1024x768 || 60Hz
|-
| 21 || 1152x864 || 75Hz
|-
| 23 || 1280x768 || 60Hz
|-
| 28 || 1280x800 || 60Hz
|-
| 32 || 1280x960 || 60Hz
|-
| 35 || 1280x1024 || 60Hz
|-
| 39 || 1360x768 || 60Hz
|-
| 42 || 1400x1050 || 60Hz
|-
| 47 || 1440x900 || 60Hz
|-
| 51 || 1600x1200 || 60Hz
|-
| 58 || 1680x1050 || 60Hz
|-
| 69 || 1920x1200 || 60Hz
|-
| 81 || 1366x768 || 60Hz
|-
| 82 || 1920x1080 (1080p) || 60Hz
|-
| 85 || 1280x720 (720p) || 60Hz
|}

Note that, at time of writing, the Raspbian X Desktop is not extended across displays. omxplayer can however play video on one screen whilst working on the other, for example:

*To play on VGA device when desktop is on HDMI device: <tt>omxplayer --display 4 test.mp4</tt>
*To play on HDMI device when desktop is on VGA device: <tt>omxplayer --display 5 test.mp4</tt>

== Comparison to Other RPi VGA Interfaces ==

This product has been designed for reliable long-term use, for example in a desktop computing environment, and as such offers proper protection to the Raspberry Pi to which it is attached given it's exposed hot-pluggable connector.

The product has been tested to:

*Conducted Emissions - EN 55032:2015
*Radiated Emissions - EN 55032:2015 (this product also meets FCC Part 15 Class B limits)
*Electrostatic Discharge - BS EN 61000-4-2 : 2009 LEVEL 4

This product provides an interference free image with the use of the RPi wireless technologies (WiFi and Bluetooth) and implements control signal TTL buffers, since the Raspberry Pi GPIOs are not able to meet VGA specifications and may be over-driven by other designs.

== Bill of Materials ==

{|class="wikitable"
!Part !! Device !! Qty !! Mouser
|-
| C1,C2,C3 || Do Not Populate || 0 ||
|-
| C4,C5 || CC0603KRX7R8BB105 || 2 || 603-CC603KRX7R8BB105
|-
| C6,C7 || CC0603KRX7R8BB224 || 2 || 603-CC603KRX7R8BB224
|-
| IC1 || CM2009-00QR || 1 || 748-CM2009-00QR
|-
| P1 || M20-7832046 || 1 || 855-M20-7832046
|-
| R1, R10, R19 || RC0603FR-07549RL || 3 || 603-RC0603FR-07549RL
|-
| R2, R11, R20 || RC0603FR-071K1L || 3 || 603-RC0603FR-071K1L
|-
| R3, R12, R21 || RC0603FR-072K2L || 3 || 603-RC0603FR-072K2L
|-
| R4, R13, R22 || RC0603FR-074K42L || 3 || 603-RC0603FR-074K42L
|-
| R5, R14, R23 || RC0603FR-078K66L || 3 || 603-RC0603FR-078K66L
|-
| R6, R15, R24 || RC0603FR-0717k4L || 3 || 603-RC0603FR-0717K4L
|-
| R7, R17, R26 || RC0603FR-0734K8L || 3 || 603-RC0603FR-0734K8L
|-
| R8, R18, R27 || RC0603FR-0769K8L || 3 || 603-RC0603FR-0769K8L
|-
| X1 || 1-1734530-1 || 1 || 571-1-1734530-1
|}

*[http://www.onsemi.com/pub_link/Collateral/CM2009-D.PDF CM2009 Datasheet]
*[http://www.mouser.com/ds/2/418/NG_CD_1734530_B3__-687281.pdf AMP 1-1734530-1 Datasheet]

== See Also ==

*[[Compliance|Product Compliance Statement]]
*[[RaspberryPi Boards]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech GPIO Interface Board rev.2

2022-07-12T19:43:42Z

James:

[[File:Lo-tech-gpio-interface-board-rev2-on-RP2.JPG|right|300px]]
The [[Lo-tech GPIO Interface Board rev.2]] enables the connection of the RaspberryPi Model A+/B+/2B/3/4 to the outside world, featuring:

*4x opto-isolated inputs (3.3 ~ 30V)
*8x open-collector outputs (3.3 ~ 30V, 200mA) with inductive drive capability
*Maxim 1-wire bus connection (eg for temperature sensor)
*Fused 5V power header (for powering the Raspberry Pi)

The board has been designed to fit directly on top of the RaspberryPi Model B+ following the HAT physical dimensions (this board does not however provide the I2C EEPROM function required for HAT auto-configuration), and is FCC Class A compliant.

'''Please [{{SERVER}}/get-in-touch/ get in touch.] for a quote for this product.''

== Specifications ==

*Small form-factor:
**Mounts directly to RaspberryPi device and fits within device footprint (65x56mm)
**2.8mm mounting holes aligned with RaspberryPi device mounting holes
**11mm spacing between boards (use 11mm standoff)
*Power Options:
**Power from GPIO header - no separate power connection required; entire device powered via micro-USB on Raspberry Pi
**5V DC provided to screw-terminals on GPIO board - no separate power connection required to the Raspberry Pi. Polyfuse protection is provided (900mA).
*Inputs:
**Four independent opto-isolated inputs with screw terminals
**Input levels: 3.3 ~ 30V
*Outputs:
**Eight Open-Collector outputs with screw terminals
**Optional pull-up resistor on outputs (can be set to 3.3V, 5V, or to external supply via COM terminal)
**Inductive Drive Capable
**Maximum operating frequency: 2MHz
*Maxim 1-wire Bus IO (screw terminals)
*Power LED
*Total assembled weight: 40g (80g, excluding screws, total when mounted on a Raspberry Pi 2)

<gallery widths="150px" heights="125px" perrow="4">
File:lo-tech-gpio-interface-board-front-rev2.jpg
File:lo-tech-gpio-interface-board-front-assembled-rev2.JPG
File:lo-tech-gpio-interface-board-back-rev2.jpg
File:lo-tech-gpio-interface-board-back-assembled-rev2.JPG
</gallery>

''Note: this board does not provide the auto-configuration capabilities defined in the [http://www.raspberrypi.org/introducing-raspberry-pi-hats/ RaspberryPi HAT specification]; GPIOs must be manually configured during program initialisation.''

== Inputs ==

''GPIO numbering follows the BCM numbering''

The board provides four inputs (GPIOs 22, 23, 24, and 27), each interfaced through [http://www.farnell.com/datasheets/1874889.pdf H11L1M opto-isolators], which feature Schmitt Trigger outputs. The inputs require 2mA drive, which should be set via appropriate value of RN1. Inputs can be up to 30V. Inputs are initialised by setting GPIOs 22, 23, 24 and 27 to input mode with pull-up. RN2 provides in-line protection to the GPIO pins.

{|class="wikitable"
!RN1 Value !!Suggested Voltage Range !!Opto Switch-On Voltage (typical) !!Opto Switch-Off Voltage (typical)
|-
|10k || 24 - 30V || 11.3V || 8.9V
|-
|6K8 || 14 - 24V || 8.1V || 6.3V
|-
|3K3 || 7 - 14V || 4.5V || 3.5V
|-
|1K5 || 5 - 7V || 2.6V || 2.2V
|-
|1K || <5V || 2.1V || 1.8V
|}

RN1 is Bourns 4608X-102 type (isolated, 8-pin 4-element)

''Note that this board does not provide transient spike protection - inputs must not exceed 30V. When using pre-production samples, do not set the input channels to output mode with this board connected, as damage to the Raspberry Pi may occur.''

== Outputs ==

''GPIO numbering follows the BCM numbering''

The board outputs are driven by a [http://www.ti.com/lit/ds/symlink/uln2803a.pdf ULN2803A Darlington Transistor Array], which is able to drive inductive loads directly and suppress the kick-back voltage via the internal free wheeling diodes (requires connection of COM terminal to external supply). Initialisation the outputs is achieved by setting GPIOs 5, 6, 12, 13, 16, 19. 20, 21, 26 to output mode.

The eight open-collector outputs are provided via screw terminals, along with GND and COM connections. Should a pull-up be required, RN3 and can added and configured via JP1 to be:

*1-2: 3V3
*2-3: 5V
*Open: when COM is connected.

JP1 '''must''' be open if external supply is connected to COM terminal - Raspberry Pi will be damaged if this is not observed. When JP1 is not open, pull-up current will be sourced from the Raspberry Pi 5V or 3V3 rails, a high value or RN3 should therefore b0e used (typically 10K).

Each output can sink 200mA; however total sink current should not exceed 600mA. ULN2803A power dissipation rules should also be observed (see [http://www.ti.com/lit/ds/symlink/uln2803a.pdf ULN2803a Datasheet]).

When driving inductive loads, external supply should be connected to COM terminal to enable internal free wheeling diodes to suppress kick-back voltage. Operating voltage should also be de-rated to ensure the maximum voltage does not exceed 30V.

== Maxim 1-wire Bus ==

The board 1-wire bus IO is directly connected to GPIO 4, along with a 4K7 pull-up. Connected temperature sensor(s) can be automatically detected by Linux with appropriate kernel modules installed. When devices are cabled, Cat5e cable is recommended.

=== Raspbian Kernel Configuration ===

For 3.18 kernel and newer, a kernel option must be added to <tt>/boot/config.txt</tt> due to change introduced with the Device Tree system (see [http://www.raspberrypi.org/forums/viewtopic.php?t=99263&p=691623 this RaspberyPi Forum Post]). Add this line to the end of the file, and reboot:

<source lang=bash>
dtoverlay=w1-gpio
</source>

Once restarted, kernel modules <tt>w1-gpio</tt> and <tt>w1-therm</tt> need to be installed:

<source lang=bash>
pi@raspberrypi ~ $ sudo modprobe w1-gpio
pi@raspberrypi ~ $ sudo modprobe w1-therm
</source>

This can be made persistent by adding these module names to <tt>/etc/modules</tt>. Sensor data is then available via <tt>/sys/bus/w1</tt>:

<source lang=bash>
pi@raspberrypi /sys/bus/w1 $ find .
.
./devices
./devices/28-000006991886
./devices/w1_bus_master1
./drivers
./drivers/w1_master_driver
./drivers/w1_master_driver/bind
./drivers/w1_master_driver/w1_bus_master1
./drivers/w1_master_driver/uevent
./drivers/w1_master_driver/unbind
./drivers/w1_slave_driver
./drivers/w1_slave_driver/bind
./drivers/w1_slave_driver/28-000006991886
./drivers/w1_slave_driver/uevent
./drivers/w1_slave_driver/unbind
./uevent
./drivers_probe
./drivers_autoprobe
</source>

For [http://datasheets.maximintegrated.com/en/ds/DS18B20.pdf Dallas 18B20 temperature sensors], <tt>28-000006991886</tt> represents the serial-number of the device (also shown in <tt>name</tt>), and the current reading is available in <tt>w1_slave</tt> (28812 in this example is 28.812°C):

<source lang=bash>
pi@raspberrypi /sys/bus/w1/devices/28-000006991886 $ cat name
28-000006991886
pi@raspberrypi /sys/bus/w1/devices/28-000006991886 $ cat w1_slave
cd 01 4b 46 7f ff 03 10 4a : crc=4a YES
cd 01 4b 46 7f ff 03 10 4a t=28812
</source>

== Bill of Materials ==

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
| C1..C5 || 0.1uF (100nF) || Ceramic Capacitor || THT || 5 || 2112751 || 581-SR205E104MAR
|-
| C6..C7 || 10uF || Electrolytic Capacitor || E2-5 || 2 || 8767084 || 647-UVR1C100MDD
|-
| C8 || Application Dependent || Electrolytic Capacitor || E2-5 || 1 || 8767084 (10uF) || 647-UVR1C100MDD (10uF)
|-
| HD1, HD2 || 10-way screw terminal (3.81mm) || FCI 20020327-D101B01LF or Kobiconn 158-P02EK381V10-E or Multicomp MC000024 || THT || 2 || 2007993 || 649-220327-D101B01LF or 158-P02EK381V10-E
|-
| HD3 || 3-way screw terminal (3.81mm) || FCI 220327-D031B01LF or Kobiconn 158-P02EK381V3-E or Multicomp MC000019 || THT || 1 || 2007986 || 649-220327-D031B01LF or 158-P02EK381V3-E
|-
| F1 || LITTELFUSE 30R135UU. POLYFUSE, PTC, 30V, RADIAL, 900MA || 30R090UU || THT || 1 || 1822234 || 576-30R135UU
|-
| IC1..IC4 || - || H11L1M Optocoupler, Schmitt Trigger || DIP-6 || 4 || 1021127 || 512-H11L1M
|-
| IC5 || - || ULN2803A Darlington Array || DIP-18 || 1 || 1094428 || 511-ULN2803A
|-
| JP1 || - || Pin Header, 1x3 || - || 1 || 1593412 || 855-M20-9990346
|-
| LED || - || 3mm LED || THT || 1 || 1581112 || 645-521-9432F (red) 859-LTL-2231AT (green)
|-
| P1 || - || SOCKET, PCB, 0.1", 20+20WAY || THT || 1 || 7992033 || 855-M20-7832046
|-
| R1 || 270R || 125mW Carbon Film Resistor || THT || 1 || 2329504 || 299-270-RC or 660-CFS1/4CT52R271G
|-
| R2 || 4k7 || 125mW Carbon Film Resistor || THT || 1 || 2329534 || 279-CFR16J4K7
|-
| RN1 || See table* || SIL-8 Resistor Network (Bournes 4608X-102 type) || THT || 1 || See tables || See tables
|-
| RN2** || 1k || 4608X-102-102LF || THT || 1 || 9356517 || 652-4608X-2LF-1K
|-
| RN3 || 10k || SIL-9 Resistor Network (Bournes 4609X-101 type) || THT || 1 || See tables || See tables
|-
| DIL Socket, 8-pin || - || SOCKET, VERTICAL, 1ROW, 8WAY || THT || 1<tt>*</tt> || 3419101 || 571-215297-8 or 571-829265-8
|-
| IC Socket (DIP18) || - || - || DIL18 || 1 || 2445623 || 571-1-2199298-5
|-
| IC Socket (DIP6) || - || - || DIL6 || 4 || 1077343 || 571-1-2199298-1
|}

<tt>*</tt>SIL sockets enable RN1 and RN3 values to be interchanged as required after construction.
<tt>**</tt>Pre-production (engineering sample) boards have RN2 unpopulated.

For values of RN1, see the table in Inputs sections. RN1 component options:

{|class="wikitable"
! Value !! Part !! Farnell !! Mouser
|-
| 1k || 4608X-102-102LF || 9356517 || 652-4608X-2LF-1K
|-
| 1k5 || 4608X-102-152LF || 9356568 || 652-4608X-2LF-1.5K
|-
| 3k3 || 4608X-102-332LF || 9356673 || 652-4608X-2LF-3.3K
|-
| 6k8 || 4608X-102-682LF || 2321777 || 652-4608X-2LF-6.8K
|-
| 10k || 4608X-102-103LF || 9356525 || 652-4608X-2LF-10K
|}

RN3 typically 10K where fitted; other values:

{|class="wikitable"
! Value !! Part !! Farnell !! Mouser
|-
| 1k || 4609X-101-102LF || 9356800 || 652-4609X-1LF-1K
|-
| 1k5 || 4609X-101-152LF || 9356851 || 652-4609X-1LF-1.5K
|-
| 3k3 || 4609X-101-332LF || 9356983 || 652-4609X-1LF-3.3K
|-
| 6k8 || 4609X-101-682LF || 2321778 || 652-4609X-1LF-6.8K
|-
| 10k || 4609X-101-103LF || 9356819 || 652-4609X-1LF-10K
|}

== Schematic & Application Notes ==

<gallery widths="300px" heights="225px" perrow="2">
File:lo-tech-GPIO-Interface-r02-Schematic.png
File:lo-tech-GPIO-Interface-r02-Application-Notes.png
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''. Copyright (c) 2014,2015 Peacon Ltd.

== Programming ==

Any library suitable for use with the Raspberry Pi (models with 40-pin GPIO header) can be used, for example [http://wiringpi.com/ WiringPi]. The module is compatible with quad-core Pi2. The GPIO channels used are:

{|class="wikitable"
!BCM GPIO !! Purpose !! Notes
|-
|4 || Maxim 1-wire Bus || Screw terminals
|-
|5 || Open-collector Output || Screw terminal output
|-
|6 || Open-collector Output || Screw terminal output
|-
|12 || Open-collector Output || Screw terminal output
|-
|13 || Open-collector Output || Screw terminal output
|-
|16 || Open-collector Output || Screw terminal output
|-
|19 || Open-collector Output || Screw terminal output
|-
|20 || Open-collector Output || Screw terminal output
|-
|22 || Input || See note
|-
|23 || Input || See note
|-
|24 || Input || See note
|-
|26 || Open-collector Output || Screw terminal output
|-
|27 || Input || See note
|}

Note: The specified H11L1M opto-isolator has an LED forward voltage of 1.2V and requires 2mA drive.

== See Also ==

*[http://www.farnell.com/datasheets/1874889.pdf H11L1M Datasheet]
*[http://www.ti.com/lit/ds/symlink/uln2803a.pdf ULN2803a Datasheet]
*[[RaspberryPi Boards]]
*[{{SERVER}}/shop Lo-tech PCB Shop]

Lo-tech Z80 CPU Test Adapter

2022-07-12T19:41:33Z

James:

[[File:Z80-CPU-Test-rev01.JPG|right|300px]]

The [[Lo-tech Z80 CPU Test Adapter]] is a simple board designed to assist with troubleshooting of Z80 based systems by enabling easy measurement of all CPU signals, and the option to present known wave-forms on all of the address bus CPU outputs.

Documentation has been developed with the kind assistance of Larry Kraemer.

''Note: this board has been discontinued.''

== Usage ==

The board provides a DIP-40 socket that should be populated with a known-good Z80 CPU. The target system CPU should then be removed, and replaced with the board. CPU orientation should be set the same as the system board.

Test probes (for logical analyser, oscilliscope, or simple multimeter) can be connected to the labelled pins to observe signals during system operation.

With the eight 2-pin headers D0 to D7 open, the mounted CPU will be isolated from the data bus and those signals held low via RN1, interpreted as NOOP instruction. Therefore the CPU will increment the program counter, and repeat - resulting in the processor attempting memory read on all of the 64KB address space continuously. The address bus signals can therefore be monitored for expected operation (square wave, with A1 having a period half that of A0, and A2 half that of A1 etc). Other signals (clock, refresh, read, mreq) can also be observed for proper operation.

With the eight 2-pin headers D0 to D7 closed, the CPU will be engaged with the data bus, and therefore normal operation should resume (once problems have been rectified!).

== Construction ==

First mount the two 20-pin headers that will be inserted into the system board CPU socket, soldering on the top side of the board (with signal names listed). In order to properly align the pins, it may be helpful to insert the headers into the un-mounted DIP socket to hold them straight. Next mount the CPU socket and remaining components, soldering on the underside.

== Testing Procedure ==

#Remove the Z80 CPU from the motherboard to be tested, and set it aside.
#Install the [[Lo-tech Z80 CPU Test Adapter]] (with a known good Z80) in the motherboard to be tested. Ensure the notch faces in the same direction as the original Z80 CPU.
#Apply power to the motherboard.
#Inspect the address lines for the wave forms listed in the table below.

If pulses are not deteced on the address lines, check the following signals:

{|class="wikitable"
!Pin !! Signal
|-
|11 || +5VDC referenced to Pin 29 (GND)
|-
|6 || Phase 0 clock
|-
|18 || HALT (should be high)
|-
|24 || WAIT (should be high)
|-
|26 || RESET (should be high)
|}

If any of these inputs are held in an incorrect state, the microprocessor will not work. Before continuing, correct any problems with these lines.

== CPU Pinout & Expected Wave Forms ==

[[File:Z80-CPU-Pinout.jpg|right|300px]]
{|class="wikitable"
! Pin !! Name !! Wave Form
|-
| 1 || A11 || xx second period square wave
|-
| 2 || A12 || xx second period square wave
|-
| 3 || A13 || xx second period square wave
|-
| 4 || A14 || xx second period square wave
|-
| 5 || A15 || xx second period square wave
|-
| 6 || *CLK ||
|-
| 7 || D4 || Tied Low
|-
| 8 || D3 || Tied Low
|-
| 9 || D5 || Tied Low
|-
| 10 || D6 || Tied Low
|-
| 11 || +5VDC ||
|-
| 12 || D2 || Tied Low
|-
| 13 || D7 || Tied Low
|-
| 14 || D0 || Tied Low
|-
| 15 || D1 || Tied Low
|-
| 16 || *INT ||
|-
| 17 || *NMI ||
|-
| 18 || *HALT ||
|-
| 19 || *MREQ ||
|-
| 20 || *IORQ ||
|-
| 21 || *RD ||
|-
| 22 || *WR ||
|-
| 23 || *BUSACK ||
|-
| 24 || *WAIT ||
|-
| 25 || *BUSRQ ||
|-
| 26 || *RESET ||
|-
| 27 || *M1 ||
|-
| 28 || *RFSH ||
|-
| 29 || GND ||
|-
| 30 || A0 || xx second period square wave
|-
| 31 || A1 || xx second period square wave
|-
| 32 || A2 || xx second period square wave
|-
| 33 || A3 || xx second period square wave
|-
| 34 || A4 || xx second period square wave
|-
| 35 || A5 || xx second period square wave
|-
| 36 || A6 || xx second period square wave
|-
| 37 || A7 || xx second period square wave
|-
| 38 || A8 || xx second period square wave
|-
| 39 || A9 || xx second period square wave
|-
| 40 || A10 || xx second period square wave
|}

== See Also ==

*[{{SERVER}}/downloads/testboards/Z80_Address_Tester.pdf Original Documentation (by Larry Kraemer)]
*[[Test Boards]]
*[http://www.lo-tech.co.uk/shop/ Lo-tech Shop]

Lo-tech TRS-80 IDE Adapter rev.2

2022-07-12T19:40:57Z

James:

[[File:Lo-tech-trs-80-ide-adapter-pcb-rev2.jpg|right|300px|lo-tech TRS-80 IDE Adapter rev.2]]
The [[Lo-tech TRS-80 IDE Adapter rev.2]] is an external IDE storage adapter for Tandy TRS-80 model 3/4/4P PCs, enabling connection of standard IDE drives (and CompactFlash cards, with an adapter). Based entirely on 7400 series logic and through-hole components, the design offers a low-cost, self-assembly storage option for these machines. The design is a minor update to the [[Lo-tech TRS-80 IDE Adapter]].

This adapter can provide bootable storage for TRS-80 Model 4P, via patched ROM - see [[#Booting|below]].

The design has experimental (i.e. untested) compatibility with the TRS-80 Model 1 and, via the Hans-01 PCB, can be used with the Model II with the replacement of one IC (see [[Using the Lo-tech TRS-80 IDE Adapter with the Model II]]).

This board can be purchased online via [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

== Technical Description ==

The adapter is connected to a TRS-80 host through the host expansion socket with a 50-wire ribbon cable, and provides access to the IDE device registers either:

*via IO ports 40-47h, for use with a suitable device driver; or
*via IO ports C8-CFh, for use with the LS-DOS (and system ROM) built-in drivers.

When used as C8h, compatibility is highly dependent on the media and may require BIOS/OS patching due to differences between ATA and the WD1010 specification (used by the TRS-80) on which it is based.

The interface is fully buffered and protected against flipped cable connection.

Similar to the [[IBM Personal Computer XT System Board Slot 8]], TRS-80 expansion cards must assert a signal to transfer data back to the host. The TRS-80 requires 33mA drive on this line (<tt>/EXTIOSEL</tt>) because of a 150-ohm pull-up resistor within the host. The [[Lo-tech TRS-80 IDE Adapter]] achieves this with 74ACT logic at U4 (U1-U3 can be LS or HCT types).

The [[Lo-tech TRS-80 IDE Adapter rev.2]] includes pull-ups on all control lines to ensure there is at least a known state on all lines at all times (and also on the unused IDE data lines).

The expansion bus on Tandy Model II devices has inverted logic on both data and address buses, but the device is otherwise compatible via the Hans-01 PCB. Compatibility is provided by:

*The Hans-01 PCB inverts the address bus via a 74LS240
*On the TRS-80-IDE PCB, 74HCT640 is used at U2 (in place of the 74HCT245N)
*Custom drivers for format routine (DOMDR6/DCT and DOMFORM6/CMD)

== Power Supply ==

Since the TRS-80 expansion port doesn't provide power, 5V DC must be supplied to the adapter. Three power supply options are provided:

*screw terminals
*mini-USB
*via the IDE header pin 20.

Note that the USB socket is only for power and should be connected to a mini-USB charger.

IDE pin 20 (the key pin) is simply connected to the Vcc (5V) line, so can be used to power the board or to supply power to an attached device (many DoM and CompactFlash adapters support pin-20 power).

== Connection Cable ==

The TRS-80 host end has a 50-pin card-edge connector which isn't keyed. A custom cable is needed, which can be constructed by attaching a 50-pin card-edge connector (search sites like Amazon or eBay for "50 Pin IDC Card Edge Connector") to a 50-wire SCSI ribbon cable.

Because of this, there's a chance that connection could be made incorrectly (with the host end flipped). In that scenario, the card is protected by referencing the state of the expansion header pin 45 (defined as no-connection) by attaching a pull-up resistor:

*When correctly connected, the pull-up generates a high logic so enabling the 74ACT241 driving /EXTIOSEL
*When incorrectly connected, the pin will be shorted to ground at the host end, hence disabling the 74ACT241 and so protecting the board from attempting to drive a high-level into a direct short to ground. The fault LED will also then be lit (if attached).

== Design ==

<gallery widths="200px" heights="150px" perrow="3">
File:lo-tech-trs-80-ide-adapter-rev2-schematic.png
File:Lo-tech-trs-80-ide-adapter-pcb-rev2.jpg
File:Lo-tech-trs-80-ide-adapter-rev2-assembled.JPG
</gallery>

Use of this design is provided subject to the '''lo-tech.co.uk [[Terms and Conditions]]'''.

=== Bill of Materials ===

{|class="wikitable"
!Part !! Value !! Device !! Package !! Qty !! Farnell !! Mouser
|-
| C1..C4 || 0.1uF (100nF) || Ceramic Capacitor || C025-024X044 || 4 || 2112751 || -
|-
| C5 || 10 - 47uF || Electrolytic Capacitor || E2-5 || 1 || 8767114 || -
|-
| C6 (see notes) || - || Ceramic Capacitor || - || - || - || -
|-
| HD1 || 2x25 Pin Boxed Header || AMPHENOL - T821150A1S100CEU || - || 1 || 2215315 || -
|-
| HD2 || 2x20 Pin Boxed Header || AMPHENOL - T821140A1S100CEU || - || 1 || 2215314 || -
|-
| JP1 || 1x2 Pin Header || AMP 826629-2 || - || 1 || 3418285 || -
|-
| LED1..LED3 || 1x2 Pin Header or 3mm LED || AMP 826629-2 or 3mm, 20mA LED || - || 3 || 3418285 or 2322126 || -
|-
| PWR1 || 1x2 Screw Terminal || MULTICOMP MC000044 || - || 1 || 2008015 || -
|-
| R1..R3 (see notes) || 150 - 300 Ohms || 250mW Carbon Film Resistor || - || 3 || 2329482 || -
|-
| R5 || 5 - 10k || 125mW Carbon Film Resistor || - || 1 || 9342419 || -
|-
| R6 || 10k || 125mW Carbon Film Resistor || - || 1 || 9342419 || -
|-
| RN1..RN3 || 10k Bussed Resistor Network || Bournes 4609X-101-103LF || SIL9 || 3 || 9356819 || -
|-
| U1 || 74HCT688N || 74HCT688N || DIL20 || 1 || 382504 || -
|-
| U2* || 74HCT640N (Model II compatibility) 74HCT245N (all others) || 74HCT640N (Model II compatibility) 74HCT245N (all others) || DIL20 || 1 || 382474 (Model II compatibility) 9591931 (all others) || -
|-
| U3 || 74HCT32N || 74HCT32N || DIL14 || 1 || 9591982 || -
|-
| U4 (see notes) || 74ACT241N || 74ACT241N || DIL20 || 1 || 1749616 || -
|-
|IC Socket (DIP20) || - || - || DIL20 || 3 || 1101349 || 571-1-390261-6
|-
|IC Socket (DIP14) || - || - || DIL14 || 1 || 1101346 || 571-1-390261-3
|-
| USB || Mini-USB Header || Molex 548190519 || THD || 1 || 9786465 || -
|}

Notes:
*U4 must be logic type ACT
*C6 can be used to increase the capacitive load on the EXTIOSEL line to increase ACT logic rise and fall time. It is not normally required and should be left unpopulated.
*LEDs can be either mounted directly on the board, or 2-pin headers fitted to enable connection to leaded LEDs, for example in a case
*R1-R3 determine LED drive; specified values provide 20mA with forward voltage drop of 1.8V across LED
*There is no R4
*All resistors have 5mm hole spacing (for 3.5mm resistors like CFR16 series). 6.8mm resistors can be mounted upright.
*Some flux helpful when soldering the USB header

<nowiki>*</nowiki>Use 74HCT245N at U2 for all hosts except Model II.

== Booting ==

A patched ROM for the TRS-80 Model 4P has been developed to enable the 4P to boot LSDOS 6.3.1 directly from the Lo-Tech TRS-80-IDE-Adapter.

See [http://bit.ly/1zKF8AV Vintage Computer Forum Development Thread] for more details and video demonstration.

This ROM and associated documentation has been developed and tested by TRS-80 enthusiasts Audronic, Gazza, and Hans, and reproduced here with their kind permission (this is not a Lo-tech product and the ROM is currently considered work-in-progress).

''Implementing the patched ROM will require dismantling of the computer, burning a new EPROM and possibly some minor modifications to the system motherboard - '''this is entirely at your own risk'''. Standard [[lo-tech.co.uk:General_disclaimer|Lo-tech Site Disclaimers]] also apply.''

*[{{SERVER}}/downloads/TRS-80-IDE/TRS-80-4P-Boot-Pack.rar Download the patched ROM binary and community documentation here]
*[{{SERVER}}/downloads/TRS-80-IDE/Model4pBootRomPinoutForFreHD.zip Download ROM Pinout documentation here]

== LDOS, LS-DOS & CP/M Drivers ==

Drivers and source have been made available with the kind permission of Firebox:

*[{{SERVER}}/downloads/TRS-80-IDE/TRS-80-IDE-Adapter-drivers-r03.zip Drivers (including source)]

== Model II Drivers ==

Drivers have been made available with the kind permission of Hans:

*[{{SERVER}}/downloads/TRS-80-IDE/Model-II-TRS80-IDE-Drivers-r01.zip Model II Drivers]

== Reference Materials ==

*[{{SERVER}}/downloads/manuals/tandy/Tandy_Model_4_and_4P_Technical_Reference_Manual_1984.pdf Tandy Model 4 Technical Reference Manual]

== See Also ==

*[[Trs-80-ide]]
*[[Lo-tech XT-CF Boards]]
*[{{SERVER}}/shop The lo-tech PCB shop]

Trs-80-ide

2022-07-12T19:40:49Z

James:

[[File:Lo-tech-trs-80-ide-adapter-pcb-rev2.jpg|right|300px|lo-tech TRS-80 IDE Adapter (rev.2)]]
The Lo-tech TRS-80 IDE Adapter is an external IDE storage adapter for Tandy TRS-80 model 3/4/4P PCs, enabling connection of standard IDE drives (and CompactFlash cards, with an adapter). Based entirely on 7400 series logic and through-hole components, the design offers a low-cost, self-assembly storage option for these machines.

The design has experimental (i.e. untested) compatibility with the TRS-80 Model 1 and, via the Hans-01 PCB, can be used with the Model II with the replacement of one IC.

These boards can be purchased online via [https://texelec.com/product-tag/lo-tech/ the TexElec Store].

== Variants ==

*[[Lo-tech TRS-80 IDE Adapter]] (first version)
*[[Lo-tech TRS-80 IDE Adapter rev.2]]

== Drivers ==

Drivers and source have been made available with the kind permission of Firebox:

*[{{SERVER}}/downloads/TRS-80-IDE/TRS-80-IDE-Adapter-drivers-r03.zip Drivers (including source)]

Lo-tech Tandy Compatible Sound Adapter

2022-07-12T19:40:22Z

James:

[[File:Lo-tech-Tandy-Sound-Adapter-r01-PCB-1024.jpg|right|300px|Lo-tech Tandy Compatible Sound Adapter PCB]]

The [[Lo-tech Tandy Compatible Sound Adapter]] is an 8-bit ISA audio board for 8-bit IBM compatible PCs providing an [https://en.wikipedia.org/wiki/Texas_Instruments_SN76489 SN76489AN] Programmable Sound Generator (PSG). The board is equipped with a simple mixer-amplifier, enabling the PSG output to be mixed with the system-board generated PC speaker sound, the combined output fed back to the internal PC Speaker or output via a 3.5mm socket to external speakers.

''Note: this board is discontinued.''

== Configuration & Resources ==

The board is configured with JP1. Two jumpers are required.

*For 0C0h (original Tandy port mapping), short pins 1-2 and 4-5
*For 1E0h (later Tandy port mapping), short 1-2 and 3-4
*For 2C0h (see note), short 2-3 and 4-5

In the [[IBM PC 5150]], ports <01Fh are reserved by IBM. It is not possible to read values from these ranges from adapters installed in the system. The [[Lo-tech Tandy Compatible Sound Adapter]] requires only write access to the SN76489AN and therefore should work, however the implementation of these ranges on clones may vary. Therefore, a 'safe' option 2C0h is also provided.

Note that it is not possible to programatically detect the presence of the SN76489AN, except perhaps by utilising the execution delay introduced by writing to the SN76489AN due to it's call on the ISA IORDY line. Software will likely need modification to utilise the SN76489AN as a 'Tandy' sound chip.

== PC Speaker Mixer ==

The IBM PC System Speaker output can be connected to the board at JP2. The header connector has the same pinout as the header on the system board, i.e. 4-pin with key. Any audio output to the PC speaker will then be mixed with output from the SN76489AN, the relative levels of the two signals controlled with VR1 (PC Speaker) and VR2 (SN76489AN). The mixed output is provided at JP3, for connection back to the system speaker, and on the 3.5mm jack for connection of external speakers (the internal speaker is silenced when external speakers are connected).

== Bill of Materials ==

{|class="wikitable"
! Part !! Description !! Part No. !! Qty !! Mouser
|-
| C1-C4, C7,C8 || 0.1uF Ceramic || K104K15X7RF53L2 || 6 || 594-K104K15X7RF53L2
|-
| C5,C6 || 47uF Electrolytic || UVR1C470MDD || 2 || 647-UVR1C470MDD
|-
| C9,C10 || 470nF Ceramic || SR205E474MAR || 2 || 581-SR205E474MAR
|-
| C11 || 47nF Ceramic || K473K15X7RF53L2 || 1 || 594-K473K15X7RF53L2
|-
| C12,C13 || 330uF Electrolytic || ECA-1CM331 || 2 || 667-ECA-1CM331
|-
| IC1 || 74LS688N || CD74HCT688E || 1 || 595-CD74HCT688E
|-
| IC2 || 74LS74N || SN74LS74AN || 1 || 595-SN74LS74AN
|-
| IC3 || SN76489AN || SN76489AN || 1 ||
|-
| IC4 || LM386N-3 || LM386N-3/NOPB || 1 || 926-LM386N-3/NOPB
|-
| JP1 || 1x05 Pinhead || 61300511121 || 1 || 710-61300511121
|-
| JP2,JP3 || 1x04 Pinhead || 61300411121 || 2 || 710-61300411121
|-
| R1 || 10R 1/4W Resistor || CFR-25JR-52-10R || 1 || 603-CFR-25JR-5210R
|-
| R2,R3 || 10K 1/8W Resistor || 270-10K-RC || 2 || 270-10K-RC
|-
| VR1,VR2 || 10K Preset Potentiometer || 36WR10KLF || 2 || 858-36WR10KLF
|-
| X1 || 3.5mm Jack || STX-3100-5N || 1 || 806-STX-3100-5N
|-
| || 2.54mm Jumper || || 2 || 806-SX1100-A
|-
| || ISA Slot Bracket || Keystone 9202 || 1 || 534-9202
|-
| || Screws || Keystone 9900 || 2 || 534-9900
|}

== Errata ==

{|class="wikitable"
||Address Decoder:
*Jumper wire required between pins 7 and 14 of IC1 (layout isolation error)
*IC1 pin 2 should be belt out (so it doesn't make contact with the socket) and jumpered to IC3 pin 5 (/IOW signal). This modification masks the Chip Select signal generated by the '688 with the ISA IOW signal because the SN76489 de-asserts READY immediately on response to Chip Select, which differs from the ISA use of this signal in response to the command (IOR, IOW, MEMR or MEMW).
||[[File:Tandy-Sound-Adapter-r01-PCB-jumper-marker.jpg|left|150px]]
|-
||Amplifier Section:
*10k pull-up resistor is required on PC speaker input 
*2k2 resistors are required in parallel to the preset potentiometers to approximate audio taper pots (otherwise level adjustment is very limited)
||[[File:Tandy-Sound-Adapter-r01-amp-mods.png|left|300px]]
|-
|}

== See Also ==

*[[Lo-tech Audio Boards]]