Tandy 1400FD Pinouts
Revision as of 14:29, 8 March 2012 by Lo-tech>James (→Signal Descriptions: Formatting error)
Pinouts for the internal and external connectors in the Tandy 1400FD are given here. For PSU pintouts, see Tandy 1400FD PSUs.
RS-232 Serial DB-9
1. Carrier Detect 6. Data Set Ready
2. Received Data 7. Request To Send
3. Transmitted Data 8. Clear To Send
4. Data Terminal Ready 9. Ring Indicate
5. Signal Ground
Printer Interface
Pin # Description Contents
1 OUTPUT STROBE STROBE signal
2 OUTPUT PDB 0 Print data bit 0
3 OUTPUT PDB 1 Print data bit 1
4 OUTPUT PDB 2 Print data bit 2
5 OUTPUT PDB 3 Print data bit 3
6 OUTPUT PDB 4 Print data bit 4
7 OUTPUT PDB 5 Print data bit 5
8 OUTPUT PDB 6 Print data bit 6
9 OUTPUT PDB 7 Print data bit 7
____
10 INPUT ACKG Printer Acknowledge
11 INPUT BUSY Printer Busy
12 INPUT PAPER END Out of paper
13 INPUT SELECT Printer select
___
14 OUTPUT ATF Auto feed
_____
15 INPUT ERROR Printer error
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16 OUTPUT INIPRN Initialize Printer
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17 OUTPUT SELINP Select input
18-25 GND
External 5-inch FDD
Pin # Contents: Pin # Contents
1 NC 15 DSEXT*
2 NC 16-23 NC
3-7 GND 24 INDEX*
8 BSIDESE 25 TRK0*
9 CDIR 26 STEP*
10 WRPRT 27 BMTRON*
11 RDDATE 28-32 GND
12 WRTATA 33-37 NC
13 WEN*
14 NC
Modem I/F Slot 20-Pin Socket
Pin # Signal Name Pin # Signal Name
1 TXDM 11 GND
2 RXDM 12 +5V
3 DTRM 13 GND
4 DSRM 14 +5V
5 CDM 15 GND
6 RIM 16 +12V
7 MODEM PWC 17 GND
8 NC 18 -12V
9 AUDIO 19 NC
10 DIRECT/ACOUSTIC 20 NC
Expansion Box I/F Slot 60-Pin Socket
Pinout
Pin # Signal Name Pin # Signal Name
1 NC 31 A19
2 +5V 32 D0
3 /ENABLE (note) 33 D1
4 NC 34 D2
5 NC 35 D3
6 /DACK0 36 GND
7 IRQ3 37 D4
8 NC 38 D5
9 GND 39 D6
10 A0 40 D7
11 A1 41 /EMW
12 A2 42 /EMR
13 A3 43 GND
14 A4 44 /EIW
15 A5 45 /EIR
16 A6 46 /TC (note)
17 A7 47 ALE
18 GND 48 /BRST
19 A8 49 /DACK1
20 A9 50 IRQ2
21 A10 51 GND
22 A11 52 +5V
23 A12 53 ECLK
24 A13 54 IRQ5
25 A14 55 DR3
26 A15 56 /DACK3
27 GND 57 BEN
28 A16 58 DR1
29 A17 59 IOREADY (note)
30 A18 60 GND (note)
Pinouts listed are from the 1400LT service manual; note that surving 1400FD documentation from radioshack.com has a number of differences:
- ENABLE and TC are listed as active-high
- AEN (pin 57, BEN) and IOREADY are listed as active-low
- Pin 60 is listed as MOTOR-ON
However it should be noted that the information in the 1400LT table is more consistent with the ISA bus standard, and that the 1400FD document lists pin 17 as "47", suggesting data may be inaccurate perhaps due to OCR error(s).
Signal Descriptions
| Signal Name | I/O | Description |
|---|---|---|
| ECLK | 0 | Clock: This is the system clock. It has 2 speed modes. (4.77MHz, 7.16MHz). The clock has a 50% duty cycle |
| /BRST | 0 | RESET: This is a the system reset. This signal is synchronized to the falling edge of clock and is active LOW |
| A0 - A19 | 0 | Address Bits 0-19: These lines are generated by either the CPU (V20) or the DMA controller (82C37). They are active HIGH. |
| D0 - D7 | 0 | Data Bits 0-7: These lines are active HIGH. |
| ALE | 0 | Address Latch Enable: This is provided by the Bus Controller (pPD71088). The CPU addresses are latched with the falling edge of ALE. |
| IOREDY | 0 | I/O Channel Ready: This line is pulled low by a memory or 1/0 device to lengthen 1/0 or memory cycle. |
| IRQ 2,3,5 | I | Interrupt Requests 2,3,5: These lines are used to signal the processor that an I/O device requires attention. |
| /EIR | 0 | I/O Read Strobe: This signal is active LOW. |
| /EIW | 0 | 1/0 Write Strobe: This signal is active LOW. |
| /EMR | 0 | Memory Read Strobe: This signal is active LOW. |
| /EMW | 0 | Memory Write Strobe: This signal is active LOW. |
| DR 1 & 3 | I | DMA Requests 1 and 3: These lines are asynchronous channel requests used by peripheral devices to gain DMA service. A request is generated by bringing DRl and, 3 lines must be held high until the corresponding DACK line goes active. |
| /DACK 0, 1 & 3 | 0 | DMA Acknowledge 0, 1 & 3: These lines are used to acknowledge DMA requests and refresh system DRAM (DACKO). They are active LOW. |
| BEN | 0 | Address Enable: This line is used to degate the CPU and other devices from the 1/0 channel to allow DMA transfers to take place. This signal is active HIGH. When this line is HIGH, the DMA Controller (82C37) has control of the lines (address bus, data bus read and write strobe: memory and I/O) |
| /TC | 0 | Terminal Count: This line provides a pulse when the terminal count for DMA channel is reached. This signal is active LOW. |
| /ENABLE | 0 | ENABLE: This line maintains a High level when internal devices are selected (ROM. RAM, VRAM, and I/O) |
| +5v | +5V +1%, -5% Max 200mA available on the bus. | |
| GND | Power Return for +5V |
Hard Disk Controller I/F Slot 60-Pin Socket
Pin # Signal Name Pin # Signal Name
1 POWER FALL 31 A19
2 +5V 32 D0
3 NC 33 D1
4 +12V 34 D2
5 +12V 35 D3
6 NC 36 GND
7 NC 37 D4
8 SHIP READY 38 D5
9 GND 39 D6
10 A0 40 D7
11 A1 41 NC
12 A2 42 /EMR
13 A3 43 GND
14 A4 44 /EIW
15 A5 45 /EIR
16 A6 46 NC
17 A7 47 NC
18 GND 48 /BRST
19 A8 49 NC
20 A9 50 NC
21 A10 51 GND
22 A11 52 +5V
23 A12 53 NC
24 A13 54 IRQ5
25 A14 55 DR3
26 A15 56 /DACK3
27 GND 57 AEN
28 A16 58 NC
29 A17 59 NC
30 A18 60 GND