8237 DMA Controller

The information is based on http://www.cs.sun.ac.za/~lraitt/doc_8237.html (which is no longer available) as reproduced http://zet.aluzina.org/index.php/8237_DMA_controller

Datasheet

The original Intel 8237A Datasheet.

Introduction

Direct memory access (DMA) facilitates data transfer operations between main memory and I/O subsystems with limited CPU intervention. The majority of I/O devices provide two methods for transferring data between a device and memory. The first method, called programmed I/O (PIO), is fairly easy to implement, but requires the processor to constantly read or write a single memory word (8-bits, 16-bits or 32-bits, depending on the device interface) until the data transfer is complete. Although PIO is not necessarily slower than DMA, it does consume more processor cycles and can be detrimental in a multi-processing environment. The second method, called DMA, allows a system to issue an I/O command to a device, initiate a DMA transaction and then place the process in a waiting queue. The system can now continue by selecting another process for execution, thereby utilizing the CPU cycles typically lost when using PIO. The DMA controller will inform the system when its current operation has been completed by issuing an interrupt signal. Although the data is still transferred 1 memory unit at a time from the device, the transfer to main memory now circumvents the CPU because the DMA controller can directly access the memory unit.

Programming the 8237

The original IBM Personal Computer 5150 shipped with an Intel 8237 DMA controller. This controller contained 4 independent 8-bit channels consisting of both an address register and counter. The later IBM PC/AT added a second 8237 in cascade mode, so extending the functionality by providing both 16-bit transfers and 4 additional channels. Some of the channels are allocated to fixed devices such as the floppy disk. Although the channels may be used with other devices, it is best to avoid situations where devices can not receive their required DMA channel. The channel assignments are presented in the following table:

Channel	Size	Usage
0	8-bit	DRAM refresh
1	8-bit	Free
2	8-bit	Floppy Disk Controller
3	8-bit	Free
4	16-bit	Cascading
5	16-bit	Free
6	16-bit	Free
7	16-bit	Free

DMA Channel Registers

Channel	I/O port	Access	Description	Channel	I/O port	Access	Description
Channel 0 (8-bit)	00H	Read/Write	Offset Register	Channel 1 (8-bit)	02H	Read/Write	Offset Register
	01H	Read/Write	Block Size Register		03H	Read/Write	Block Size Register
	87H	Write only	Page Register		83H	Write only	Page Register
Channel 2 (8-bit)	04H	Read/Write	Offset Register	Channel 3 (8-bit)	06H	Read/Write	Offset Register
	05H	Read/Write	Block Size Register		07H	Read/Write	Block Size Register
	81H	Write only	Page Register		82H	Write only	Page Register
Channel 4 (16-bit)	C0H	Read/Write	Offset Register	Channel 5 (16-bit)	C4H	Read/Write	Offset Register
	C2H	Read/Write	Block Size Register		C6H	Read/Write	Block Size Register
	8FH	Write only	Page Register		8BH	Write only	Page Register
Channel 6 (16-bit)	C8H	Read/Write	Offset Register	Channel 7 (16-bit)	CCH	Read/Write	Offset Register
	CAH	Read/Write	Block Size Register		CEH	Read/Write	Block Size Register
	89H	Write only	Page Register		8AH	Write only	Page Register

Miscellaneous Registers

Primary Controller			Secondary Controller
I/O port	Access	Description	I/O port	Access	Description
08H	Read/Write	Command and Status Register	D0H	Read/Write	Command and Status Register
09H	Write only	Request Register	D2H	Write only	Request Register
0AH	Write only	Single Mask Register	D4H	Write only	Single Mask Register
0BH	Write only	Mode Register	D6H	Write only	Mode Register
0CH	Write only	Clear Flip-Flop Register	D8H	Write only	Clear Flip-Flop Register
0DH	Write only	Master Reset Register	DAH	Write only	Master Reset Register
0EH	Write only	Master Enable Register	DCH	Write only	Master Enable Register
0FH	Write only	Master Mask Register	DEH	Write only	Master Mask Register

Mode Register

7	6	5	4	3	2	1	0
MODE		INC	AI	TYPE		CHANNEL

Bits 6 and 7 are used to select the transfer mode: 00b = Demand mode, 01b = Single mode, 10b = Block mode, 11b = Cascade mode
Setting INC selects address decrement, clearing INC selects address increment
Setting AI enables auto-initialization
Bits 2 and 3 are used to select the transfer type: 00b = Verify, 01b = Write to memory, 10b = Read from memory, 11b = Undefined
Bits 0 and 1 are used to select the channel: 00b = channel 0, 01b = channel 1 10b = channel 2 and 11b = channel 3

Single Mask Register

7	6	5	4	3	2	1	0
Unused					SRST	CHANNEL

SRST (Set/Reset Mask) = 1 disables the selected channel. SRST = 0 will enable the selected channel
Bits 0 and 1 are used to select the channel: 00b = channel 0, 01b = channel 1, 10b = channel 2 and 11b = channel 3

Block Size/Countdown Register

The Block Size/Countdown Register is 16-bits wide for both 8-bit and 16-bit DMA operations. However, the I/O port is only 8-bits wide and will require two successive read or write operations to the I/O port. The low order bits must be sent first, followed by the high order bits of the block length when writing to this I/O port. The length of the block being transferred, decremented by 1, can be set by writing to this I/O port. Reading from this I/O port returns the remaining block size, decremented by 1. The value of the Countdown Register will be set to -1 when a transfer has been completed. For 16-bit transactions, the value written to the countdown register is the number of 16-bit word transfers.

Offset Register

The Offset Register is 16-bits wide for both 8-bit and 16-bit DMA operations and contains the starting offset of the buffer used in the DMA transaction. The low order bits must be sent first, followed by the high order bits of the offset when writing to this register. For 16-bit transactions, the value written to the offset register must be aligned on a 16-bit boundary.

Page Registers

The Page Register specifies the base address of the page in memory where the DMA buffer resides. A page can be either 64K (8-bit transactions) or 128K (16-bit transaction) in size. The Page Register is very similar to the Segment Registers used by the PC to compute a physical address. For 8-bit transactions, only the lower 4 bits of the page register is used, thereby restricting the DMA buffer to reside below the first 1Mb of memory (address of buffer SHR 16).

Initiating a DMA transaction

Initiating a DMA transaction is quite simple and only requires the following steps:

Save the current interrupt status and disable interrupts by executing the CLI instruction
Disable the channel that will be used for the transaction
Reset the flip-flop by writing a value of 0X to the register
Set the Mode Register
Set the Page Register
Set the Offset Register
Set the Block Size Register
Enable the channel that will be used for the transaction
Restore the interrupt status

Example: I/O to Memory Transfer

In this example, we will consider a DMA transfer from an I/O device (the diskette drive) to memory, also referred to as a DMA write operation.

The diskette driver receives a request to read data from a specific sector and transfer the information to a specific buffer. The diskette drive uses DMA channel 2, which means that the DMA buffer must fall within the first 1MB of memory (newer controllers allow all eight channels to access memory within the first 16MB) and can not exceed 64K, nor cross a 64K page. We will assume that the diskette driver has already allocated a suitable DMA buffer as part of its initialization.
The diskette driver now performs the necessary operations to position its read/write head on the correct sector and track before sending the necessary information to the DMA controller including the following:
- The base address in memory where the DMA buffer is located.
- The number of bytes to transfer minus one.
- The offset within the buffer.
- The DMA operation (in this case a write operation).
The diskette driver updates the DMA mask to allow recognition of DMA channel 2 requests before sending the read command to the diskette controller. In a multi-processing operating system, the kernel will block the user process that requested the diskette operation and schedule a new process for execution.
The diskette drive, under the supervision of its controller card, will begin to read data from the diskette surface before transferring it to its data register. Once data becomes available, the diskette controller will request DMA service by asserting a high on DMA request line 2 (DREQ2).
The DMA controller verifies that DREQ2 may be allowed (by examining its mask register) and requests the CPU to enter a hold mode. This is done by asserting the hold request line (HRQ).
The CPU will respond by asserting hold acknowledge (HLDA) and now enters a bus holding state.
The DMA controller will generate an address before passing it to the bus and activating the memory write and I/O read control lines. The DMA acknowledge signal (DACK2) is activated to inform the diskette controller that the DMA transfer is in progress.
The data is transferred from the diskette controller's data register to memory without passing through the DMA controller. After every transfer, the DMA controller will decrement the countdown register associated with channel 2. During the transfer, the CPU effectively shares the bus with the diskette controller by interleaving bus hold cycles and normal cycles under the supervision of the DMA controller (sometime referred to as cycle stealing).
If the transfer completes, the DMA controller will assert the terminal count line signal (TC). Note that the DMA controller may temporarily stop the transfer by dropping DREQ2 if the transfer rate is too fast to handle. The TC signal indicates to the diskette controller that the operation has been completed and the HRQ and DACK2 lines are deactivated before dropping DREQ2.
At this point the CPU will resume normal bus control, but the diskette controller will signal the operating system through the PIC that the operation is complete by asserting IRQ6. Control will typically be transferred to the interrupt handler of the diskette driver to verify the controller results before copying the data from the DMA buffer to the buffer supplied by the user processes.